[Qemu-devel] [PATCH v2 0/3] qdev'ify PReP PCI host bridge

[Qemu-devel] [PATCH v2 0/3] qdev'ify PReP PCI host bridge

[Andreas Färber]

Hello Anthony and Hervé,

Here's my rebased qdev'ification of PReP PCI host.

It is tested not to make things worse than they are already.

I've split up my original patch and did some renaming to make it better readable.
Please compare it to yours; it is intended to go in before the second QOM series.

Some not immediately needed changes, such as adding the IRQs as state to the SysBus
device (Hervé's patch) and dropping pci_prep_init() in favor of sysbus_create_simple()
are deferred to the 40P machine series.

Regards,
Andreas

Changes since v1:
* Use the new .vendor_id etc. in PCIDeviceInfo
* Rename from PRePPCI to Raven, adopt naming scheme from i440FX
* Rebase onto multiple Memory API conversions
* Split into PCIDevice and SysBus patches, leave out PREPPCIState changes
http://patchwork.ozlabs.org/patch/100268/

Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Alexander Graf <agraf@suse.de>
Cc: Anthony Liguori <aliguori@us.ibm.com>

Andreas Färber (3):
  prep: qdev'ify Raven host bridge
  prep: Add Raven PCI host SysBus device
  MAINTAINERS: Add PCI host bridge files to PReP machine

 MAINTAINERS   |    1 +
 hw/prep_pci.c |   88 +++++++++++++++++++++++++++++++++++++++++++++++----------
 2 files changed, 74 insertions(+), 15 deletions(-)

-- 
1.7.7

[Qemu-devel] [PATCH v2 1/3] prep: qdev'ify Raven host bridge

[Andreas Färber]

Move initialization of vendor ID, etc. to PCIDeviceInfo.
Add VMState.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>
---
 hw/prep_pci.c |   55 ++++++++++++++++++++++++++++++++++++++++++++++---------
 1 files changed, 46 insertions(+), 9 deletions(-)

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index ea9fb69..741b273 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -29,6 +29,10 @@
 
 typedef PCIHostState PREPPCIState;
 
+typedef struct RavenPCIState {
+    PCIDevice dev;
+} RavenPCIState;
+
 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
 {
     int i;
@@ -111,7 +115,6 @@ PCIBus *pci_prep_init(qemu_irq *pic,
                       MemoryRegion *address_space_io)
 {
     PREPPCIState *s;
-    PCIDevice *d;
 
     s = g_malloc0(sizeof(PREPPCIState));
     s->bus = pci_register_bus(NULL, "pci",
@@ -133,16 +136,50 @@ PCIBus *pci_prep_init(qemu_irq *pic,
     memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
     memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg);
 
-    /* PCI host bridge */
-    d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
-                            sizeof(PCIDevice), 0, NULL, NULL);
-    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
-    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
-    d->config[0x08] = 0x00; // revision
-    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
+    pci_create_simple(s->bus, 0, "raven");
+
+    return s->bus;
+}
+
+static int raven_init(PCIDevice *d)
+{
     d->config[0x0C] = 0x08; // cache_line_size
     d->config[0x0D] = 0x10; // latency_timer
     d->config[0x34] = 0x00; // capabilities_pointer
 
-    return s->bus;
+    return 0;
 }
+
+static const VMStateDescription vmstate_raven = {
+    .name = "raven",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(dev, RavenPCIState),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static PCIDeviceInfo raven_info = {
+    .qdev.name = "raven",
+    .qdev.desc = "PReP Host Bridge - Motorola Raven",
+    .qdev.size = sizeof(RavenPCIState),
+    .qdev.vmsd = &vmstate_raven,
+    .qdev.no_user = 1,
+    .no_hotplug = 1,
+    .init = raven_init,
+    .vendor_id = PCI_VENDOR_ID_MOTOROLA,
+    .device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN,
+    .revision = 0x00,
+    .class_id = PCI_CLASS_BRIDGE_HOST,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_END_OF_LIST()
+    },
+};
+
+static void raven_register_devices(void)
+{
+    pci_qdev_register(&raven_info);
+}
+
+device_init(raven_register_devices)
-- 
1.7.7

Re: [Qemu-devel] [PATCH v2 1/3] prep: qdev'ify Raven host bridge

[Anthony Liguori]

On 01/06/2012 06:06 PM, Andreas Färber wrote:
> Move initialization of vendor ID, etc. to PCIDeviceInfo.
> Add VMState.
>
> Signed-off-by: Andreas Färber<andreas.faerber@web.de>
> Cc: Hervé Poussineau<hpoussin@reactos.org>
> Cc: Michael S. Tsirkin<mst@redhat.com>
> Cc: Anthony Liguori<aliguori@us.ibm.com>
> ---
>   hw/prep_pci.c |   55 ++++++++++++++++++++++++++++++++++++++++++++++---------
>   1 files changed, 46 insertions(+), 9 deletions(-)
>
> diff --git a/hw/prep_pci.c b/hw/prep_pci.c
> index ea9fb69..741b273 100644
> --- a/hw/prep_pci.c
> +++ b/hw/prep_pci.c
> @@ -29,6 +29,10 @@
>
>   typedef PCIHostState PREPPCIState;
>
> +typedef struct RavenPCIState {
> +    PCIDevice dev;
> +} RavenPCIState;
> +
>   static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
>   {
>       int i;
> @@ -111,7 +115,6 @@ PCIBus *pci_prep_init(qemu_irq *pic,
>                         MemoryRegion *address_space_io)
>   {
>       PREPPCIState *s;
> -    PCIDevice *d;
>
>       s = g_malloc0(sizeof(PREPPCIState));
>       s->bus = pci_register_bus(NULL, "pci",
> @@ -133,16 +136,50 @@ PCIBus *pci_prep_init(qemu_irq *pic,
>       memory_region_init_io(&s->mmcfg,&PPC_PCIIO_ops, s, "pciio", 0x00400000);
>       memory_region_add_subregion(address_space_mem, 0x80800000,&s->mmcfg);
>
> -    /* PCI host bridge */
> -    d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
> -                            sizeof(PCIDevice), 0, NULL, NULL);
> -    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
> -    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
> -    d->config[0x08] = 0x00; // revision
> -    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
> +    pci_create_simple(s->bus, 0, "raven");
> +
> +    return s->bus;
> +}
> +
> +static int raven_init(PCIDevice *d)
> +{
>       d->config[0x0C] = 0x08; // cache_line_size
>       d->config[0x0D] = 0x10; // latency_timer
>       d->config[0x34] = 0x00; // capabilities_pointer
>
> -    return s->bus;
> +    return 0;
>   }
> +
> +static const VMStateDescription vmstate_raven = {
> +    .name = "raven",
> +    .version_id = 0,
> +    .minimum_version_id = 0,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_PCI_DEVICE(dev, RavenPCIState),
> +        VMSTATE_END_OF_LIST()
> +    },
> +};
> +
> +static PCIDeviceInfo raven_info = {
> +    .qdev.name = "raven",
> +    .qdev.desc = "PReP Host Bridge - Motorola Raven",
> +    .qdev.size = sizeof(RavenPCIState),
> +    .qdev.vmsd =&vmstate_raven,
> +    .qdev.no_user = 1,
> +    .no_hotplug = 1,
> +    .init = raven_init,
> +    .vendor_id = PCI_VENDOR_ID_MOTOROLA,
> +    .device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN,
> +    .revision = 0x00,
> +    .class_id = PCI_CLASS_BRIDGE_HOST,
> +    .qdev.props = (Property[]) {
> +        DEFINE_PROP_END_OF_LIST()
> +    },
> +};
> +
> +static void raven_register_devices(void)
> +{
> +    pci_qdev_register(&raven_info);
> +}
> +
> +device_init(raven_register_devices)


How can the host bridge itself be a PCI device?  What we do for the i440fx is 
have a i440fx-pcihost device which is a SysBusDevice and then a create a 
separate PCIDevice (i440fx) which acts as the host device config space.

Regards,

Anthony Liguori

[Qemu-devel] [PATCH v2 2/3] prep: Add Raven PCI host SysBus device

[Andreas Färber]

For now, focus on qdev'ification and leave PIC IRQs unchanged.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>
---
 hw/prep_pci.c |   41 +++++++++++++++++++++++++++++++----------
 1 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 741b273..2ff6b8c 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -114,31 +114,43 @@ PCIBus *pci_prep_init(qemu_irq *pic,
                       MemoryRegion *address_space_mem,
                       MemoryRegion *address_space_io)
 {
+    DeviceState *dev;
     PREPPCIState *s;
 
-    s = g_malloc0(sizeof(PREPPCIState));
-    s->bus = pci_register_bus(NULL, "pci",
+    dev = qdev_create(NULL, "raven-pcihost");
+    s = FROM_SYSBUS(PREPPCIState, sysbus_from_qdev(dev));
+    s->address_space = address_space_mem;
+    s->bus = pci_register_bus(&s->busdev.qdev, "pci",
                               prep_set_irq, prep_map_irq, pic,
                               address_space_mem,
                               address_space_io,
                               0, 4);
+    qdev_init_nofail(dev);
+    qdev_property_add_child(qdev_get_root(), "raven", dev, NULL);
+
+    memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
+    memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg);
+
+    pci_create_simple(s->bus, 0, "raven");
+
+    return s->bus;
+}
+
+static int raven_pcihost_init(SysBusDevice *dev)
+{
+    PREPPCIState *s = FROM_SYSBUS(PREPPCIState, dev);
 
     memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s,
                           "pci-conf-idx", 1);
-    memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
+    sysbus_add_io(dev, 0xcf8, &s->conf_mem);
     sysbus_init_ioports(&s->busdev, 0xcf8, 1);
 
     memory_region_init_io(&s->data_mem, &pci_host_data_be_ops, s,
                           "pci-conf-data", 1);
-    memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
+    sysbus_add_io(dev, 0xcfc, &s->data_mem);
     sysbus_init_ioports(&s->busdev, 0xcfc, 1);
 
-    memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
-    memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg);
-
-    pci_create_simple(s->bus, 0, "raven");
-
-    return s->bus;
+    return 0;
 }
 
 static int raven_init(PCIDevice *d)
@@ -177,8 +189,17 @@ static PCIDeviceInfo raven_info = {
     },
 };
 
+static SysBusDeviceInfo raven_pcihost_info = {
+    .qdev.name = "raven-pcihost",
+    .qdev.fw_name = "pci",
+    .qdev.size = sizeof(PREPPCIState),
+    .qdev.no_user = 1,
+    .init = raven_pcihost_init,
+};
+
 static void raven_register_devices(void)
 {
+    sysbus_register_withprop(&raven_pcihost_info);
     pci_qdev_register(&raven_info);
 }
 
-- 
1.7.7

Re: [Qemu-devel] [PATCH v2 2/3] prep: Add Raven PCI host SysBus device

[Anthony Liguori]

On 01/06/2012 06:06 PM, Andreas Färber wrote:
> For now, focus on qdev'ification and leave PIC IRQs unchanged.
>
> Signed-off-by: Andreas Färber<andreas.faerber@web.de>
> Cc: Hervé Poussineau<hpoussin@reactos.org>
> Cc: Michael S. Tsirkin<mst@redhat.com>
> Cc: Anthony Liguori<aliguori@us.ibm.com>
> ---
>   hw/prep_pci.c |   41 +++++++++++++++++++++++++++++++----------
>   1 files changed, 31 insertions(+), 10 deletions(-)
>
> diff --git a/hw/prep_pci.c b/hw/prep_pci.c
> index 741b273..2ff6b8c 100644
> --- a/hw/prep_pci.c
> +++ b/hw/prep_pci.c
> @@ -114,31 +114,43 @@ PCIBus *pci_prep_init(qemu_irq *pic,
>                         MemoryRegion *address_space_mem,
>                         MemoryRegion *address_space_io)
>   {
> +    DeviceState *dev;
>       PREPPCIState *s;
>
> -    s = g_malloc0(sizeof(PREPPCIState));
> -    s->bus = pci_register_bus(NULL, "pci",
> +    dev = qdev_create(NULL, "raven-pcihost");
> +    s = FROM_SYSBUS(PREPPCIState, sysbus_from_qdev(dev));
> +    s->address_space = address_space_mem;
> +    s->bus = pci_register_bus(&s->busdev.qdev, "pci",
>                                 prep_set_irq, prep_map_irq, pic,
>                                 address_space_mem,
>                                 address_space_io,
>                                 0, 4);
> +    qdev_init_nofail(dev);
> +    qdev_property_add_child(qdev_get_root(), "raven", dev, NULL);
> +
> +    memory_region_init_io(&s->mmcfg,&PPC_PCIIO_ops, s, "pciio", 0x00400000);
> +    memory_region_add_subregion(address_space_mem, 0x80800000,&s->mmcfg);
> +
> +    pci_create_simple(s->bus, 0, "raven");
> +
> +    return s->bus;
> +}
> +
> +static int raven_pcihost_init(SysBusDevice *dev)
> +{
> +    PREPPCIState *s = FROM_SYSBUS(PREPPCIState, dev);
>
>       memory_region_init_io(&s->conf_mem,&pci_host_conf_be_ops, s,
>                             "pci-conf-idx", 1);
> -    memory_region_add_subregion(address_space_io, 0xcf8,&s->conf_mem);
> +    sysbus_add_io(dev, 0xcf8,&s->conf_mem);
>       sysbus_init_ioports(&s->busdev, 0xcf8, 1);
>
>       memory_region_init_io(&s->data_mem,&pci_host_data_be_ops, s,
>                             "pci-conf-data", 1);
> -    memory_region_add_subregion(address_space_io, 0xcfc,&s->data_mem);
> +    sysbus_add_io(dev, 0xcfc,&s->data_mem);
>       sysbus_init_ioports(&s->busdev, 0xcfc, 1);
>
> -    memory_region_init_io(&s->mmcfg,&PPC_PCIIO_ops, s, "pciio", 0x00400000);
> -    memory_region_add_subregion(address_space_mem, 0x80800000,&s->mmcfg);
> -
> -    pci_create_simple(s->bus, 0, "raven");
> -
> -    return s->bus;
> +    return 0;
>   }
>
>   static int raven_init(PCIDevice *d)
> @@ -177,8 +189,17 @@ static PCIDeviceInfo raven_info = {
>       },
>   };
>
> +static SysBusDeviceInfo raven_pcihost_info = {
> +    .qdev.name = "raven-pcihost",
> +    .qdev.fw_name = "pci",
> +    .qdev.size = sizeof(PREPPCIState),
> +    .qdev.no_user = 1,
> +    .init = raven_pcihost_init,
> +};
> +
>   static void raven_register_devices(void)
>   {
> +    sysbus_register_withprop(&raven_pcihost_info);
>       pci_qdev_register(&raven_info);

I see now :-)  Ignore previous message.

Regards,

Anthony Liguori

>   }
>

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 2/3] prep: Add Raven PCI host SysBus device

[Alexander Graf]

On 07.01.2012, at 01:06, Andreas Färber wrote:

> For now, focus on qdev'ification and leave PIC IRQs unchanged.
> 
> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
> Cc: Hervé Poussineau <hpoussin@reactos.org>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: Anthony Liguori <aliguori@us.ibm.com>
> ---
> hw/prep_pci.c |   41 +++++++++++++++++++++++++++++++----------
> 1 files changed, 31 insertions(+), 10 deletions(-)
> 
> diff --git a/hw/prep_pci.c b/hw/prep_pci.c
> index 741b273..2ff6b8c 100644
> --- a/hw/prep_pci.c
> +++ b/hw/prep_pci.c
> @@ -114,31 +114,43 @@ PCIBus *pci_prep_init(qemu_irq *pic,
>                       MemoryRegion *address_space_mem,
>                       MemoryRegion *address_space_io)
> {

I'm not sure this is the best way to do this. For e500, we just create the host bridge explicitly in the board file:

    /* PCI */
    dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
                                mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
                                mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
                                NULL);
    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
    if (!pci_bus)
        printf("couldn't create PCI controller!\n");

and that's all the interaction there is between the pci host code and the board code. No calling into functions. The way you're doing it now, the board still needs to call into prep_pci.c which doesn't sound too appealing to me :).

> +    DeviceState *dev;
>     PREPPCIState *s;
> 
> -    s = g_malloc0(sizeof(PREPPCIState));
> -    s->bus = pci_register_bus(NULL, "pci",
> +    dev = qdev_create(NULL, "raven-pcihost");
> +    s = FROM_SYSBUS(PREPPCIState, sysbus_from_qdev(dev));
> +    s->address_space = address_space_mem;
> +    s->bus = pci_register_bus(&s->busdev.qdev, "pci",
>                               prep_set_irq, prep_map_irq, pic,
>                               address_space_mem,
>                               address_space_io,
>                               0, 4);

This should be happening in the host bridge init code. Take a look at e500_pcihost_initfn() in hw/ppce500_pci.c.


Alex

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 2/3] prep: Add Raven PCI host SysBus device

[Andreas Färber]

Am 11.01.2012 23:12, schrieb Alexander Graf:
> 
> On 07.01.2012, at 01:06, Andreas Färber wrote:
> 
>> For now, focus on qdev'ification and leave PIC IRQs unchanged.
>>
>> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
>> Cc: Hervé Poussineau <hpoussin@reactos.org>
>> Cc: Michael S. Tsirkin <mst@redhat.com>
>> Cc: Anthony Liguori <aliguori@us.ibm.com>
>> ---
>> hw/prep_pci.c |   41 +++++++++++++++++++++++++++++++----------
>> 1 files changed, 31 insertions(+), 10 deletions(-)
>>
>> diff --git a/hw/prep_pci.c b/hw/prep_pci.c
>> index 741b273..2ff6b8c 100644
>> --- a/hw/prep_pci.c
>> +++ b/hw/prep_pci.c
>> @@ -114,31 +114,43 @@ PCIBus *pci_prep_init(qemu_irq *pic,
>>                       MemoryRegion *address_space_mem,
>>                       MemoryRegion *address_space_io)
>> {
> 
> I'm not sure this is the best way to do this. For e500, we just create the host bridge explicitly in the board file:
> 
>     /* PCI */
>     dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
>                                 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
>                                 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
>                                 NULL);
>     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
>     if (!pci_bus)
>         printf("couldn't create PCI controller!\n");
> 
> and that's all the interaction there is between the pci host code and the board code. No calling into functions. The way you're doing it now, the board still needs to call into prep_pci.c which doesn't sound too appealing to me :).

That's a TODO for a later patch. As you can see, those lines were not
introduced in this series. For the PCI-ISA bridge, we need to get rid of
qemu_irq *pic anyway - that's what the commit message refers to. Should
clarify that, thanks.

>> +    DeviceState *dev;
>>     PREPPCIState *s;
>>
>> -    s = g_malloc0(sizeof(PREPPCIState));
>> -    s->bus = pci_register_bus(NULL, "pci",
>> +    dev = qdev_create(NULL, "raven-pcihost");
>> +    s = FROM_SYSBUS(PREPPCIState, sysbus_from_qdev(dev));
>> +    s->address_space = address_space_mem;
>> +    s->bus = pci_register_bus(&s->busdev.qdev, "pci",
>>                               prep_set_irq, prep_map_irq, pic,
>>                               address_space_mem,
>>                               address_space_io,
>>                               0, 4);
> 
> This should be happening in the host bridge init code. Take a look at e500_pcihost_initfn() in hw/ppce500_pci.c.

I don't see how that could work for PReP: prep_set_irq and prep_map_irq
need the IRQs allocated by the i8259 on the upcoming i82378 PCI-ISA
bridge, which as a PCIDevice needs the PCI host bridge set up already...

To allow for board-specific setup (prep vs. 40p) v2 uses pci_bus_new()
there and uses pci_bus_irqs() on the board. :)

Andreas

[Qemu-devel] [PATCH v2 3/3] MAINTAINERS: Add PCI host bridge files to PReP machine

[Andreas Färber]

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 MAINTAINERS |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 764c92d..6e9cd33 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -307,6 +307,7 @@ PReP
 M: Andreas Färber <andreas.faerber@web.de>
 S: Odd Fixes
 F: hw/ppc_prep.c
+F: hw/prep_pci.[hc]
 
 SH4 Machines
 ------------
-- 
1.7.7

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 3/3] MAINTAINERS: Add PCI host bridge files to PReP machine

[Alexander Graf]

On 07.01.2012, at 01:06, Andreas Färber wrote:

> Signed-off-by: Andreas Färber <andreas.faerber@web.de>

Acked-by: Alexander Graf <agraf@suse.de>


Alex

> ---
> MAINTAINERS |    1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 764c92d..6e9cd33 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -307,6 +307,7 @@ PReP
> M: Andreas Färber <andreas.faerber@web.de>
> S: Odd Fixes
> F: hw/ppc_prep.c
> +F: hw/prep_pci.[hc]
> 
> SH4 Machines
> ------------
> -- 
> 1.7.7
> 
> 

[Qemu-devel] [PATCH v3 0/8] qdev'ify PReP PCI host bridge and add PCI-to-ISA bridge

[Andreas Färber]

Hello,

Here's an updated initial qdev'ification series for PReP, as prerequisite
for Anthony's second QOM series.

As stated before, this is NOT a complete conversion of all PReP devices
and of all those shared with x86. Please comment on what's there, not on
what may be done, too. I'm sitting on these patches for over a year now,
so let's start getting some of it merged so that we can move on with QOM
and get some of the design issues fixed that kept the pc87312 Super I/O
and 40P machine from getting merged in the first place!

Regards,
Andreas

Changes since v2:
* Simplify I/O byte swaps.
* Convert I/O from old_mmio to MemoryRegion ops.
* Drop pci_prep_init() and instantiate the PCI host bridge in the machine,
  reintroducing PREPPCIState extension.
* Connect IRQs via qdev after instantiating. Suggested by Alex.
* Add a rebased PCI-to-ISA-bridge from the 40P series on top, to show why
  some suggestions from v2 and IRC don't work out.
  * Merge fix-up by Hervé: Add indirection for late-connected out[0] IRQ.
  * Add VMState for i82374 and i82378.
  * From i82378 drop the I/O address translation duplicated from the board.
  * Rebase i82378 onto Memory API.
  http://patchwork.ozlabs.org/patch/100250/
  http://patchwork.ozlabs.org/patch/100272/
* Add new patch from Hervé to wire up the PCI-to-ISA bridge for 'prep'.

Changes since v1:
* Use the new .vendor_id etc. in PCIDeviceInfo
* Rename from PRePPCI to Raven, adopt naming scheme from i440FX
* Rebase onto multiple Memory API conversions
* Split into PCIDevice and SysBus patches, leave out PREPPCIState changes
http://patchwork.ozlabs.org/patch/100268/

Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Anthony Liguori <aliguori@us.ibm.com>
Cc: Alexander Graf <agraf@suse.de>

Andreas Färber (8):
  prep: qdev'ify Raven host bridge (PCIDevice)
  prep_pci: Simplify I/O endianness
  prep_pci: Update I/O to MemoryRegion ops
  prep: qdev'ify Raven host bridge (SysBus)
  MAINTAINERS: Add PCI host bridge files to PReP machine
  prep: Add i82374 DMA emulation
  prep: Add i82378 PCI-to-ISA bridge emulation
  prep: Use i82378 PCI->ISA bridge for 'prep' machine

 MAINTAINERS                     |    1 +
 Makefile.objs                   |    2 +
 default-configs/ppc-softmmu.mak |    3 +
 hw/i82374.c                     |  154 ++++++++++++++++++++++++
 hw/i82378.c                     |  252 +++++++++++++++++++++++++++++++++++++++
 hw/pci_ids.h                    |    1 +
 hw/ppc_prep.c                   |   77 +++++-------
 hw/prep_pci.c                   |  181 +++++++++++++++++-----------
 hw/prep_pci.h                   |   11 --
 9 files changed, 553 insertions(+), 129 deletions(-)
 create mode 100644 hw/i82374.c
 create mode 100644 hw/i82378.c
 delete mode 100644 hw/prep_pci.h

-- 
1.7.7

[Qemu-devel] [PATCH v3 1/8] prep: qdev'ify Raven host bridge (PCIDevice)

[Andreas Färber]

Move initialization of vendor ID, etc. to PCIDeviceInfo.
Introduce VMState.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Anthony Liguori <aliguori@us.ibm.com>
---
 hw/prep_pci.c |   55 ++++++++++++++++++++++++++++++++++++++++++++++---------
 1 files changed, 46 insertions(+), 9 deletions(-)

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index ea9fb69..741b273 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -29,6 +29,10 @@
 
 typedef PCIHostState PREPPCIState;
 
+typedef struct RavenPCIState {
+    PCIDevice dev;
+} RavenPCIState;
+
 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
 {
     int i;
@@ -111,7 +115,6 @@ PCIBus *pci_prep_init(qemu_irq *pic,
                       MemoryRegion *address_space_io)
 {
     PREPPCIState *s;
-    PCIDevice *d;
 
     s = g_malloc0(sizeof(PREPPCIState));
     s->bus = pci_register_bus(NULL, "pci",
@@ -133,16 +136,50 @@ PCIBus *pci_prep_init(qemu_irq *pic,
     memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
     memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg);
 
-    /* PCI host bridge */
-    d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
-                            sizeof(PCIDevice), 0, NULL, NULL);
-    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
-    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
-    d->config[0x08] = 0x00; // revision
-    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
+    pci_create_simple(s->bus, 0, "raven");
+
+    return s->bus;
+}
+
+static int raven_init(PCIDevice *d)
+{
     d->config[0x0C] = 0x08; // cache_line_size
     d->config[0x0D] = 0x10; // latency_timer
     d->config[0x34] = 0x00; // capabilities_pointer
 
-    return s->bus;
+    return 0;
 }
+
+static const VMStateDescription vmstate_raven = {
+    .name = "raven",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(dev, RavenPCIState),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static PCIDeviceInfo raven_info = {
+    .qdev.name = "raven",
+    .qdev.desc = "PReP Host Bridge - Motorola Raven",
+    .qdev.size = sizeof(RavenPCIState),
+    .qdev.vmsd = &vmstate_raven,
+    .qdev.no_user = 1,
+    .no_hotplug = 1,
+    .init = raven_init,
+    .vendor_id = PCI_VENDOR_ID_MOTOROLA,
+    .device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN,
+    .revision = 0x00,
+    .class_id = PCI_CLASS_BRIDGE_HOST,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_END_OF_LIST()
+    },
+};
+
+static void raven_register_devices(void)
+{
+    pci_qdev_register(&raven_info);
+}
+
+device_init(raven_register_devices)
-- 
1.7.7

[Qemu-devel] [PATCH v3 2/8] prep_pci: Simplify I/O endianness

[Andreas Färber]

The prep PowerPC CPU is Big Endian. An explicit byte swap therefore
effectively becomes Little Endian.

Remove explicit byte swaps and mark as Little Endian.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Alexander Graf <agraf@suse.de>
Cc: Michael S. Tsirkin <mst@redhat.com>
---
 hw/prep_pci.c |    6 +-----
 1 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 741b273..edfb25d 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -53,14 +53,12 @@ static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t va
 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     PREPPCIState *s = opaque;
-    val = bswap16(val);
     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
 }
 
 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     PREPPCIState *s = opaque;
-    val = bswap32(val);
     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
 }
 
@@ -77,7 +75,6 @@ static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
     PREPPCIState *s = opaque;
     uint32_t val;
     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
-    val = bswap16(val);
     return val;
 }
 
@@ -86,7 +83,6 @@ static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
     PREPPCIState *s = opaque;
     uint32_t val;
     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
-    val = bswap32(val);
     return val;
 }
 
@@ -95,7 +91,7 @@ static const MemoryRegionOps PPC_PCIIO_ops = {
         .read = { PPC_PCIIO_readb, PPC_PCIIO_readw, PPC_PCIIO_readl, },
         .write = { PPC_PCIIO_writeb, PPC_PCIIO_writew, PPC_PCIIO_writel, },
     },
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
-- 
1.7.7

[Qemu-devel] [PATCH v3 3/8] prep_pci: Update I/O to MemoryRegion ops

[Andreas Färber]

Convert to new-style read/write callbacks.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Avi Kivity <avi@redhat.com>
Cc: Benoît Canet <benoit.canet@gmail.com>
---
 hw/prep_pci.c |   61 +++++++++++++++++++++-----------------------------------
 1 files changed, 23 insertions(+), 38 deletions(-)

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index edfb25d..5970196 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -44,53 +44,38 @@ static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
     return (addr & 0x7ff) |  (i << 11);
 }
 
-static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
+static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
+                             uint64_t val, unsigned int size)
 {
     PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
-}
-
-static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
-}
-
-static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
-}
-
-static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
-{
-    PREPPCIState *s = opaque;
-    uint32_t val;
-    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
-    return val;
-}
-
-static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
-{
-    PREPPCIState *s = opaque;
-    uint32_t val;
-    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
-    return val;
+    switch (size) {
+    case 1:
+    case 2:
+    case 4:
+        pci_data_write(s->bus, PPC_PCIIO_config(addr), val, size);
+        break;
+    default:
+        abort();
+    }
 }
 
-static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
+                                unsigned int size)
 {
     PREPPCIState *s = opaque;
-    uint32_t val;
-    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
-    return val;
+    switch (size) {
+    case 1:
+    case 2:
+    case 4:
+        return pci_data_read(s->bus, PPC_PCIIO_config(addr), size);
+    default:
+        abort();
+    }
 }
 
 static const MemoryRegionOps PPC_PCIIO_ops = {
-    .old_mmio = {
-        .read = { PPC_PCIIO_readb, PPC_PCIIO_readw, PPC_PCIIO_readl, },
-        .write = { PPC_PCIIO_writeb, PPC_PCIIO_writew, PPC_PCIIO_writel, },
-    },
+    .read = ppc_pci_io_read,
+    .write = ppc_pci_io_write,
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-- 
1.7.7

Re: [Qemu-devel] [PATCH v3 3/8] prep_pci: Update I/O to MemoryRegion ops

[Avi Kivity]

On 01/13/2012 05:09 AM, Andreas Färber wrote:
> Convert to new-style read/write callbacks.
>
>  
> -static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
> +static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
> +                                unsigned int size)
>  {
>      PREPPCIState *s = opaque;
> -    uint32_t val;
> -    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
> -    return val;
> +    switch (size) {
> +    case 1:
> +    case 2:
> +    case 4:
> +        return pci_data_read(s->bus, PPC_PCIIO_config(addr), size);
> +    default:
> +        abort();
> +    }
>  }

Huh? just call pci_data_read() unconditionally.

-- 
error compiling committee.c: too many arguments to function

Re: [Qemu-devel] [PATCH v3 3/8] prep_pci: Update I/O to MemoryRegion ops

[Andreas Färber]

Am 15.01.2012 10:19, schrieb Avi Kivity:
> On 01/13/2012 05:09 AM, Andreas Färber wrote:
>> Convert to new-style read/write callbacks.
>>
>>  
>> -static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
>> +static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
>> +                                unsigned int size)
>>  {
>>      PREPPCIState *s = opaque;
>> -    uint32_t val;
>> -    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
>> -    return val;
>> +    switch (size) {
>> +    case 1:
>> +    case 2:
>> +    case 4:
>> +        return pci_data_read(s->bus, PPC_PCIIO_config(addr), size);
>> +    default:
>> +        abort();
>> +    }
>>  }
> 
> Huh? just call pci_data_read() unconditionally.

Just so that I understand, is that because PReP is 32-bit ppc? In the
above mechanical conversion, size 8 would abort.

BTW did we agree on an indentation style for switch?

Andreas

Re: [Qemu-devel] [PATCH v3 3/8] prep_pci: Update I/O to MemoryRegion ops

[Avi Kivity]

On 01/16/2012 05:08 PM, Andreas Färber wrote:
> Am 15.01.2012 10:19, schrieb Avi Kivity:
> > On 01/13/2012 05:09 AM, Andreas Färber wrote:
> >> Convert to new-style read/write callbacks.
> >>
> >>  
> >> -static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
> >> +static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
> >> +                                unsigned int size)
> >>  {
> >>      PREPPCIState *s = opaque;
> >> -    uint32_t val;
> >> -    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
> >> -    return val;
> >> +    switch (size) {
> >> +    case 1:
> >> +    case 2:
> >> +    case 4:
> >> +        return pci_data_read(s->bus, PPC_PCIIO_config(addr), size);
> >> +    default:
> >> +        abort();
> >> +    }
> >>  }
> > 
> > Huh? just call pci_data_read() unconditionally.
>
> Just so that I understand, is that because PReP is 32-bit ppc? In the
> above mechanical conversion, size 8 would abort.

The memory core never issues size 8 transactions, since the code is
unprepared for it.  When we will support it, you'll have to explicitly
declare it with .impl.max_access_size = 8 or something.

> BTW did we agree on an indentation style for switch?

What you wrote conforms to the de facto standard.

-- 
error compiling committee.c: too many arguments to function

[Qemu-devel] [PATCH v3 4/8] prep: qdev'ify Raven host bridge (SysBus)

[Andreas Färber]

Drop pci_prep_init() in favor of extended device state. Inspired by
patches from Hervé and Alex.

Assign the 4 IRQs from the board after device instantiation. This moves
the knowledge out of prep_pci and allows for future machines with
different IRQ wiring (IBM 40P). Suggested by Alex.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Alexander Graf <agraf@suse.de>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>
---
 hw/ppc_prep.c |   23 +++++++++++++++++-
 hw/prep_pci.c |   67 +++++++++++++++++++++++++++++++++++---------------------
 hw/prep_pci.h |   11 ---------
 3 files changed, 63 insertions(+), 38 deletions(-)
 delete mode 100644 hw/prep_pci.h

diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index dec059a..747539f 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -29,7 +29,7 @@
 #include "sysemu.h"
 #include "isa.h"
 #include "pci.h"
-#include "prep_pci.h"
+#include "pci_host.h"
 #include "usb-ohci.h"
 #include "ppc.h"
 #include "boards.h"
@@ -522,6 +522,9 @@ static void ppc_prep_init (ram_addr_t ram_size,
     MemoryRegion *bios = g_new(MemoryRegion, 1);
     uint32_t kernel_base, initrd_base;
     long kernel_size, initrd_size;
+    DeviceState *dev;
+    SysBusDevice *sys;
+    PCIHostState *pcihost;
     PCIBus *pci_bus;
     ISABus *isa_bus;
     qemu_irq *i8259;
@@ -633,7 +636,23 @@ static void ppc_prep_init (ram_addr_t ram_size,
     /* Hmm, prep has no pci-isa bridge ??? */
     isa_bus = isa_bus_new(NULL, get_system_io());
     i8259 = i8259_init(isa_bus, first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
-    pci_bus = pci_prep_init(i8259, get_system_memory(), get_system_io());
+
+    dev = qdev_create(NULL, "raven-pcihost");
+    sys = sysbus_from_qdev(dev);
+    pcihost = DO_UPCAST(PCIHostState, busdev, sys);
+    pcihost->address_space = get_system_memory();
+    qdev_init_nofail(dev);
+    qdev_property_add_child(qdev_get_root(), "raven", dev, NULL);
+    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
+    if (pci_bus == NULL) {
+        fprintf(stderr, "Couldn't create PCI host controller.\n");
+        exit(1);
+    }
+    sysbus_connect_irq(&pcihost->busdev, 0, i8259[9]);
+    sysbus_connect_irq(&pcihost->busdev, 1, i8259[11]);
+    sysbus_connect_irq(&pcihost->busdev, 2, i8259[9]);
+    sysbus_connect_irq(&pcihost->busdev, 3, i8259[11]);
+
     isa_bus_irqs(isa_bus, i8259);
     //    pci_bus = i440fx_init();
     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 5970196..ccd0832 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -25,9 +25,12 @@
 #include "hw.h"
 #include "pci.h"
 #include "pci_host.h"
-#include "prep_pci.h"
+#include "exec-memory.h"
 
-typedef PCIHostState PREPPCIState;
+typedef struct PRePPCIState {
+    PCIHostState host_state;
+    qemu_irq irq[4];
+} PREPPCIState;
 
 typedef struct RavenPCIState {
     PCIDevice dev;
@@ -52,7 +55,7 @@ static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
     case 1:
     case 2:
     case 4:
-        pci_data_write(s->bus, PPC_PCIIO_config(addr), val, size);
+        pci_data_write(s->host_state.bus, PPC_PCIIO_config(addr), val, size);
         break;
     default:
         abort();
@@ -67,7 +70,7 @@ static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
     case 1:
     case 2:
     case 4:
-        return pci_data_read(s->bus, PPC_PCIIO_config(addr), size);
+        return pci_data_read(s->host_state.bus, PPC_PCIIO_config(addr), size);
     default:
         abort();
     }
@@ -88,38 +91,43 @@ static void prep_set_irq(void *opaque, int irq_num, int level)
 {
     qemu_irq *pic = opaque;
 
-    qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
+    qemu_set_irq(pic[irq_num] , level);
 }
 
-PCIBus *pci_prep_init(qemu_irq *pic,
-                      MemoryRegion *address_space_mem,
-                      MemoryRegion *address_space_io)
+static int raven_pcihost_init(SysBusDevice *dev)
 {
-    PREPPCIState *s;
+    PCIHostState *h = FROM_SYSBUS(PCIHostState, dev);
+    PREPPCIState *s = DO_UPCAST(PREPPCIState, host_state, h);
+    MemoryRegion *address_space_mem = get_system_memory();
+    MemoryRegion *address_space_io = get_system_io();
+    PCIBus *bus;
+    int i;
+
+    for (i = 0; i < 4; i++) {
+        sysbus_init_irq(dev, &s->irq[i]);
+    }
 
-    s = g_malloc0(sizeof(PREPPCIState));
-    s->bus = pci_register_bus(NULL, "pci",
-                              prep_set_irq, prep_map_irq, pic,
-                              address_space_mem,
-                              address_space_io,
-                              0, 4);
+    bus = pci_register_bus(&h->busdev.qdev, NULL,
+                           prep_set_irq, prep_map_irq, s->irq,
+                           address_space_mem, address_space_io, 0, 4);
+    h->bus = bus;
 
-    memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s,
+    memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, s,
                           "pci-conf-idx", 1);
-    memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
-    sysbus_init_ioports(&s->busdev, 0xcf8, 1);
+    sysbus_add_io(dev, 0xcf8, &h->conf_mem);
+    sysbus_init_ioports(&h->busdev, 0xcf8, 1);
 
-    memory_region_init_io(&s->data_mem, &pci_host_data_be_ops, s,
+    memory_region_init_io(&h->data_mem, &pci_host_data_be_ops, s,
                           "pci-conf-data", 1);
-    memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
-    sysbus_init_ioports(&s->busdev, 0xcfc, 1);
+    sysbus_add_io(dev, 0xcfc, &h->data_mem);
+    sysbus_init_ioports(&h->busdev, 0xcfc, 1);
 
-    memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
-    memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg);
+    memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
+    memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 
-    pci_create_simple(s->bus, 0, "raven");
+    pci_create_simple(bus, 0, "raven");
 
-    return s->bus;
+    return 0;
 }
 
 static int raven_init(PCIDevice *d)
@@ -158,8 +166,17 @@ static PCIDeviceInfo raven_info = {
     },
 };
 
+static SysBusDeviceInfo raven_pcihost_info = {
+    .qdev.name = "raven-pcihost",
+    .qdev.fw_name = "pci",
+    .qdev.size = sizeof(PREPPCIState),
+    .qdev.no_user = 1,
+    .init = raven_pcihost_init,
+};
+
 static void raven_register_devices(void)
 {
+    sysbus_register_withprop(&raven_pcihost_info);
     pci_qdev_register(&raven_info);
 }
 
diff --git a/hw/prep_pci.h b/hw/prep_pci.h
deleted file mode 100644
index b6b481a..0000000
--- a/hw/prep_pci.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef QEMU_PREP_PCI_H
-#define QEMU_PREP_PCI_H
-
-#include "qemu-common.h"
-#include "memory.h"
-
-PCIBus *pci_prep_init(qemu_irq *pic,
-                      MemoryRegion *address_space_mem,
-                      MemoryRegion *address_space_io);
-
-#endif
-- 
1.7.7

[Qemu-devel] [PATCH v3 5/8] MAINTAINERS: Add PCI host bridge files to PReP machine

[Andreas Färber]

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Acked-by: Alexander Graf <agraf@suse.de>
---
 MAINTAINERS |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index de2a916..148f0d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -307,6 +307,7 @@ PReP
 M: Andreas Färber <andreas.faerber@web.de>
 S: Odd Fixes
 F: hw/ppc_prep.c
+F: hw/prep_pci.[hc]
 
 SH4 Machines
 ------------
-- 
1.7.7

[Qemu-devel] [PATCH v3 6/8] prep: Add i82374 DMA emulation

[Andreas Färber]

Prepare Intel 82374 emulation for use by Intel 82378 PCI->ISA bridge.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Confine to CONFIG_I82374. Add VMState.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 Makefile.objs                   |    1 +
 default-configs/ppc-softmmu.mak |    1 +
 hw/i82374.c                     |  154 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 156 insertions(+), 0 deletions(-)
 create mode 100644 hw/i82374.c

diff --git a/Makefile.objs b/Makefile.objs
index 4f6d26c..26af1f2 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -215,6 +215,7 @@ hw-obj-$(CONFIG_FDC) += fdc.o
 hw-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o
 hw-obj-$(CONFIG_APM) += pm_smbus.o apm.o
 hw-obj-$(CONFIG_DMA) += dma.o
+hw-obj-$(CONFIG_I82374) += i82374.o
 hw-obj-$(CONFIG_HPET) += hpet.o
 hw-obj-$(CONFIG_APPLESMC) += applesmc.o
 hw-obj-$(CONFIG_SMARTCARD) += usb-ccid.o ccid-card-passthru.o
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index c85cdce..e5905d5 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -11,6 +11,7 @@ CONFIG_I8254=y
 CONFIG_PCKBD=y
 CONFIG_FDC=y
 CONFIG_DMA=y
+CONFIG_I82374=y
 CONFIG_OPENPIC=y
 CONFIG_PREP_PCI=y
 CONFIG_MACIO=y
diff --git a/hw/i82374.c b/hw/i82374.c
new file mode 100644
index 0000000..616d1fc
--- /dev/null
+++ b/hw/i82374.c
@@ -0,0 +1,154 @@
+/*
+ * QEMU Intel 82374 emulation (Enhanced DMA controller)
+ *
+ * Copyright (c) 2010 Hervé Poussineau
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "isa.h"
+
+//#define DEBUG_I82374
+
+#ifdef DEBUG_I82374
+#define DPRINTF(fmt, ...) \
+do { fprintf(stderr, "i82374: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) \
+do {} while (0)
+#endif
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "i82374 ERROR: " fmt , ## __VA_ARGS__); } while (0)
+
+typedef struct I82374State {
+    uint8_t commands[8];
+} I82374State;
+
+static const VMStateDescription vmstate_i82374 = {
+    .name = "i82374",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8_ARRAY(commands, I82374State, 8),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static uint32_t i82374_read_isr(void *opaque, uint32_t nport)
+{
+    uint32_t val = 0;
+
+    BADF("%s: %08x\n", __func__, nport);
+
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
+    return val;
+}
+
+static void i82374_write_command(void *opaque, uint32_t nport, uint32_t data)
+{
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
+
+    if (data != 0x42) {
+        /* Not Stop S/G command */
+        BADF("%s: %08x=%08x\n", __func__, nport, data);
+    }
+}
+
+static uint32_t i82374_read_status(void *opaque, uint32_t nport)
+{
+    uint32_t val = 0;
+
+    BADF("%s: %08x\n", __func__, nport);
+
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
+    return val;
+}
+
+static void i82374_write_descriptor(void *opaque, uint32_t nport, uint32_t data)
+{
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
+
+    BADF("%s: %08x=%08x\n", __func__, nport, data);
+}
+
+static uint32_t i82374_read_descriptor(void *opaque, uint32_t nport)
+{
+    uint32_t val = 0;
+
+    BADF("%s: %08x\n", __func__, nport);
+
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
+    return val;
+}
+
+static void i82374_init(I82374State *s)
+{
+    DMA_init(1, NULL);
+    memset(s->commands, 0, sizeof(s->commands));
+}
+
+typedef struct ISAi82374State {
+    ISADevice dev;
+    uint32_t iobase;
+    I82374State state;
+} ISAi82374State;
+
+static const VMStateDescription vmstate_isa_i82374 = {
+    .name = "isa-i82374",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_STRUCT(state, ISAi82374State, 0, vmstate_i82374, I82374State),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static int i82374_isa_init(ISADevice *dev)
+{
+    ISAi82374State *isa = DO_UPCAST(ISAi82374State, dev, dev);
+    I82374State *s = &isa->state;
+
+    register_ioport_read(isa->iobase + 0x0A, 1, 1, i82374_read_isr, s);
+    register_ioport_write(isa->iobase + 0x10, 8, 1, i82374_write_command, s);
+    register_ioport_read(isa->iobase + 0x18, 8, 1, i82374_read_status, s);
+    register_ioport_write(isa->iobase + 0x20, 0x20, 1, i82374_write_descriptor, s);
+    register_ioport_read(isa->iobase + 0x20, 0x20, 1, i82374_read_descriptor, s);
+
+    i82374_init(s);
+
+    return 0;
+}
+
+static ISADeviceInfo i82374_isa_info = {
+    .qdev.name  = "i82374",
+    .qdev.size  = sizeof(ISAi82374State),
+    .qdev.vmsd  = &vmstate_isa_i82374,
+    .init       = i82374_isa_init,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_HEX32("iobase", ISAi82374State, iobase, 0x400),
+        DEFINE_PROP_END_OF_LIST()
+    },
+};
+
+static void i82374_register_devices(void)
+{
+    isa_qdev_register(&i82374_isa_info);
+}
+
+device_init(i82374_register_devices)
-- 
1.7.7

[Qemu-devel] [PATCH v3 7/8] prep: Add i82378 PCI-to-ISA bridge emulation

[Andreas Färber]

Prepare Intel 82378 emulation for use by PReP platforms.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Create ISA bus in this device (suggested by Markus).
Rebase onto Memory API, mark memory ops as Little Endian.
Add VMState.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Markus Armbruster <armbru@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
---
 Makefile.objs                   |    1 +
 default-configs/ppc-softmmu.mak |    2 +
 hw/i82378.c                     |  252 +++++++++++++++++++++++++++++++++++++++
 hw/pci_ids.h                    |    1 +
 4 files changed, 256 insertions(+), 0 deletions(-)
 create mode 100644 hw/i82378.c

diff --git a/Makefile.objs b/Makefile.objs
index 26af1f2..656ae62 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -225,6 +225,7 @@ hw-obj-$(CONFIG_I8259) += i8259.o
 
 # PPC devices
 hw-obj-$(CONFIG_PREP_PCI) += prep_pci.o
+hw-obj-$(CONFIG_I82378) += i82378.o
 # Mac shared devices
 hw-obj-$(CONFIG_MACIO) += macio.o
 hw-obj-$(CONFIG_CUDA) += cuda.o
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index e5905d5..1fe9c6d 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -14,7 +14,9 @@ CONFIG_DMA=y
 CONFIG_I82374=y
 CONFIG_OPENPIC=y
 CONFIG_PREP_PCI=y
+CONFIG_I82378=y
 CONFIG_MACIO=y
+CONFIG_PCSPK=y
 CONFIG_CUDA=y
 CONFIG_ADB=y
 CONFIG_MAC_NVRAM=y
diff --git a/hw/i82378.c b/hw/i82378.c
new file mode 100644
index 0000000..3808a90
--- /dev/null
+++ b/hw/i82378.c
@@ -0,0 +1,252 @@
+/*
+ * QEMU Intel i82378 emulation (PCI to ISA bridge)
+ *
+ * Copyright (c) 2010-2011 Hervé Poussineau
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "pci.h"
+#include "pc.h"
+
+//#define DEBUG_I82378
+
+#ifdef DEBUG_I82378
+#define DPRINTF(fmt, ...) \
+do { fprintf(stderr, "i82378: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) \
+do {} while (0)
+#endif
+
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "i82378 ERROR: " fmt , ## __VA_ARGS__); } while (0)
+
+typedef struct I82378State {
+    qemu_irq out[2];
+    MemoryRegion io;
+    MemoryRegion mem;
+} I82378State;
+
+typedef struct PCIi82378State {
+    PCIDevice pci_dev;
+    uint32_t isa_io_base;
+    uint32_t isa_mem_base;
+    I82378State state;
+} PCIi82378State;
+
+static const VMStateDescription vmstate_pci_i82378 = {
+    .name = "pci-i82378",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(pci_dev, PCIi82378State),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static void i82378_io_write(void *opaque, target_phys_addr_t addr,
+                            uint64_t value, unsigned int size)
+{
+    switch (size) {
+    case 1:
+        DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outb(addr, value);
+        break;
+    case 2:
+        DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outw(addr, value);
+        break;
+    case 4:
+        DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outl(addr, value);
+        break;
+    default:
+        abort();
+    }
+}
+
+static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
+                               unsigned int size)
+{
+    DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
+    switch (size) {
+    case 1:
+        return cpu_inb(addr);
+    case 2:
+        return cpu_inw(addr);
+    case 4:
+        return cpu_inl(addr);
+    default:
+        abort();
+    }
+}
+
+static const MemoryRegionOps i82378_io_ops = {
+    .read = i82378_io_read,
+    .write = i82378_io_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
+                             uint64_t value, unsigned int size)
+{
+    switch (size) {
+    case 1:
+        DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outb(addr, value);
+        break;
+    case 2:
+        DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outw(addr, value);
+        break;
+    case 4:
+        DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outl(addr, value);
+        break;
+    default:
+        abort();
+    }
+}
+
+static uint64_t i82378_mem_read(void *opaque, target_phys_addr_t addr,
+                                unsigned int size)
+{
+    DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
+    switch (size) {
+    case 1:
+        return cpu_inb(addr);
+    case 2:
+        return cpu_inw(addr);
+    case 4:
+        return cpu_inl(addr);
+    default:
+        abort();
+    }
+}
+
+static const MemoryRegionOps i82378_mem_ops = {
+    .read = i82378_mem_read,
+    .write = i82378_mem_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void i82378_request_out0_irq(void *opaque, int irq, int level)
+{
+    I82378State *s = opaque;
+    qemu_set_irq(s->out[0], level);
+}
+
+static void i82378_init(DeviceState *dev, I82378State *s)
+{
+    ISABus *isabus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(dev, "isa.0"));
+    ISADevice *pit;
+    qemu_irq *out0_irq;
+
+    /* This device has:
+       2 82C59 (irq)
+       1 82C54 (pit)
+       2 82C37 (dma)
+       NMI
+       Utility Bus Support Registers
+
+       All devices accept byte access only, except timer
+     */
+
+    qdev_init_gpio_out(dev, s->out, 2);
+
+    /* Workaround the fact that i8259 is not qdev'ified... */
+    out0_irq = qemu_allocate_irqs(i82378_request_out0_irq, s, 1);
+
+    /* 2 82C59 (irq) */
+    isa_bus_irqs(isabus, i8259_init(isabus, *out0_irq));
+
+    /* 1 82C54 (pit) */
+    pit = pit_init(isabus, 0x40, 0);
+
+    /* speaker */
+    pcspk_init(pit);
+
+    /* 2 82C37 (dma) */
+    DMA_init(1, &s->out[1]);
+    isa_create_simple(isabus, "i82374");
+
+    /* timer */
+    isa_create_simple(isabus, "mc146818rtc");
+}
+
+static int pci_i82378_init(PCIDevice *dev)
+{
+    PCIi82378State *pci = DO_UPCAST(PCIi82378State, pci_dev, dev);
+    I82378State *s = &pci->state;
+    uint8_t *pci_conf;
+
+    pci_conf = dev->config;
+    pci_set_word(pci_conf + PCI_COMMAND,
+                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+    pci_set_word(pci_conf + PCI_STATUS,
+                 PCI_STATUS_DEVSEL_MEDIUM);
+
+    pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
+
+    memory_region_init_io(&s->io, &i82378_io_ops, s, "i82378-io", 0x00010000);
+    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io);
+
+    memory_region_init_io(&s->mem, &i82378_mem_ops, s, "i82378-mem", 0x01000000);
+    memory_region_set_coalescing(&s->mem);
+    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
+
+    /* Make I/O address read only */
+    pci_set_word(dev->wmask + PCI_COMMAND, PCI_COMMAND_SPECIAL);
+    pci_set_long(dev->wmask + PCI_BASE_ADDRESS_0, 0);
+    pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, pci->isa_io_base);
+
+    isa_mem_base = pci->isa_mem_base;
+    isa_bus_new(&dev->qdev, pci_address_space_io(dev));
+
+    i82378_init(&dev->qdev, s);
+
+    return 0;
+}
+
+static PCIDeviceInfo pci_i82378_info = {
+    .init = pci_i82378_init,
+    .qdev.name = "i82378",
+    .qdev.size = sizeof(PCIi82378State),
+    .qdev.vmsd = &vmstate_pci_i82378,
+    .vendor_id = PCI_VENDOR_ID_INTEL,
+    .device_id = PCI_DEVICE_ID_INTEL_82378,
+    .revision = 0x03,
+    .class_id = PCI_CLASS_BRIDGE_ISA,
+    .subsystem_vendor_id = 0x0,
+    .subsystem_id = 0x0,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_HEX32("iobase", PCIi82378State, isa_io_base, 0x80000000),
+        DEFINE_PROP_HEX32("membase", PCIi82378State, isa_mem_base, 0xc0000000),
+        DEFINE_PROP_END_OF_LIST()
+    },
+};
+
+static void i82378_register_devices(void)
+{
+    pci_qdev_register(&pci_i82378_info);
+}
+
+device_init(i82378_register_devices)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 83f3893..0fd643f 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -98,6 +98,7 @@
 #define PCI_DEVICE_ID_MPC8533E           0x0030
 
 #define PCI_VENDOR_ID_INTEL              0x8086
+#define PCI_DEVICE_ID_INTEL_82378        0x0484
 #define PCI_DEVICE_ID_INTEL_82441        0x1237
 #define PCI_DEVICE_ID_INTEL_82801AA_5    0x2415
 #define PCI_DEVICE_ID_INTEL_82801D       0x24CD
-- 
1.7.7

[Qemu-devel] [PATCH v3 8/8] prep: Use i82378 PCI->ISA bridge for 'prep' machine

[Andreas Färber]

Speaker I/O, ISA bus, i8259 PIC, RTC and DMA are no longer set up
individually by the machine. Effectively, no-op speaker I/O is replaced
by pcspk; PIT and i82374 DMA are introduced.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Remove related dead, alternative code.
Access i8259 IRQs via ISA bus to resolve cyclic dependency with PCI
host bridge.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Alexander Graf <agraf@suse.de>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
---
 hw/ppc_prep.c |   54 +++++++++++-------------------------------------------
 1 files changed, 11 insertions(+), 43 deletions(-)

diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 747539f..9485d45 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -83,37 +83,9 @@ static const int ide_irq[2] = { 13, 13 };
 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 
-//static ISADevice *pit;
-
 /* ISA IO ports bridge */
 #define PPC_IO_BASE 0x80000000
 
-#if 0
-/* Speaker port 0x61 */
-static int speaker_data_on;
-static int dummy_refresh_clock;
-#endif
-
-static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
-{
-#if 0
-    speaker_data_on = (val >> 1) & 1;
-    pit_set_gate(pit, 2, val & 1);
-#endif
-}
-
-static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
-{
-#if 0
-    int out;
-    out = pit_get_out(pit, 2, qemu_get_clock_ns(vm_clock));
-    dummy_refresh_clock ^= 1;
-    return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
-        (dummy_refresh_clock << 4);
-#endif
-    return 0;
-}
-
 /* PCI intack register */
 /* Read-only register (?) */
 static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
@@ -526,6 +498,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
     SysBusDevice *sys;
     PCIHostState *pcihost;
     PCIBus *pci_bus;
+    PCIDevice *pci;
     ISABus *isa_bus;
     qemu_irq *i8259;
     qemu_irq *cpu_exit_irq;
@@ -629,13 +602,9 @@ static void ppc_prep_init (ram_addr_t ram_size,
         }
     }
 
-    isa_mem_base = 0xc0000000;
     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
         hw_error("Only 6xx bus is supported on PREP machine\n");
     }
-    /* Hmm, prep has no pci-isa bridge ??? */
-    isa_bus = isa_bus_new(NULL, get_system_io());
-    i8259 = i8259_init(isa_bus, first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 
     dev = qdev_create(NULL, "raven-pcihost");
     sys = sysbus_from_qdev(dev);
@@ -648,13 +617,21 @@ static void ppc_prep_init (ram_addr_t ram_size,
         fprintf(stderr, "Couldn't create PCI host controller.\n");
         exit(1);
     }
+
+    /* PCI -> ISA bridge */
+    pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
+    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
+    qdev_connect_gpio_out(&pci->qdev, 0,
+                          first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
+    qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
+    isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
+
+    i8259 = isa_bus->irqs;
     sysbus_connect_irq(&pcihost->busdev, 0, i8259[9]);
     sysbus_connect_irq(&pcihost->busdev, 1, i8259[11]);
     sysbus_connect_irq(&pcihost->busdev, 2, i8259[9]);
     sysbus_connect_irq(&pcihost->busdev, 3, i8259[11]);
 
-    isa_bus_irqs(isa_bus, i8259);
-    //    pci_bus = i440fx_init();
     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
     memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
                           "ppc-io", 0x00800000);
@@ -662,9 +639,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
 
     /* init basic PC hardware */
     pci_vga_init(pci_bus);
-    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
-    //    pit = pit_init(0x40, 0);
-    rtc_init(isa_bus, 2000, NULL);
 
     if (serial_hds[0])
         serial_isa_init(isa_bus, 0, serial_hds[0]);
@@ -691,9 +665,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
     }
     isa_create_simple(isa_bus, "i8042");
 
-    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
-    DMA_init(1, cpu_exit_irq);
-
     //    SB16_init();
 
     for(i = 0; i < MAX_FD; i++) {
@@ -701,9 +672,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
     }
     fdctrl_init_isa(isa_bus, fd);
 
-    /* Register speaker port */
-    register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
-    register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
     /* Register fake IO ports for PREP */
     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
-- 
1.7.7

Re: [Qemu-devel] [PATCH v3 8/8] prep: Use i82378 PCI->ISA bridge for 'prep' machine

[Jan Kiszka]

On 2012-01-13 04:09, Andreas Färber wrote:
> Speaker I/O, ISA bus, i8259 PIC, RTC and DMA are no longer set up
> individually by the machine. Effectively, no-op speaker I/O is replaced
> by pcspk; PIT and i82374 DMA are introduced.
> 
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> 
> Remove related dead, alternative code.
> Access i8259 IRQs via ISA bus to resolve cyclic dependency with PCI
> host bridge.
> 
> Signed-off-by: Andreas Färber <andreas.faerber@web.de>
> Cc: Alexander Graf <agraf@suse.de>
> Cc: Jan Kiszka <jan.kiszka@siemens.com>
> ---
>  hw/ppc_prep.c |   54 +++++++++++-------------------------------------------
>  1 files changed, 11 insertions(+), 43 deletions(-)
> 
> diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
> index 747539f..9485d45 100644
> --- a/hw/ppc_prep.c
> +++ b/hw/ppc_prep.c
> @@ -83,37 +83,9 @@ static const int ide_irq[2] = { 13, 13 };
>  static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
>  static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
>  
> -//static ISADevice *pit;
> -
>  /* ISA IO ports bridge */
>  #define PPC_IO_BASE 0x80000000
>  
> -#if 0
> -/* Speaker port 0x61 */
> -static int speaker_data_on;
> -static int dummy_refresh_clock;
> -#endif
> -
> -static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
> -{
> -#if 0
> -    speaker_data_on = (val >> 1) & 1;
> -    pit_set_gate(pit, 2, val & 1);
> -#endif
> -}
> -
> -static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
> -{
> -#if 0
> -    int out;
> -    out = pit_get_out(pit, 2, qemu_get_clock_ns(vm_clock));
> -    dummy_refresh_clock ^= 1;
> -    return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
> -        (dummy_refresh_clock << 4);
> -#endif
> -    return 0;
> -}
> -
>  /* PCI intack register */
>  /* Read-only register (?) */
>  static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
> @@ -526,6 +498,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
>      SysBusDevice *sys;
>      PCIHostState *pcihost;
>      PCIBus *pci_bus;
> +    PCIDevice *pci;
>      ISABus *isa_bus;
>      qemu_irq *i8259;
>      qemu_irq *cpu_exit_irq;
> @@ -629,13 +602,9 @@ static void ppc_prep_init (ram_addr_t ram_size,
>          }
>      }
>  
> -    isa_mem_base = 0xc0000000;
>      if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
>          hw_error("Only 6xx bus is supported on PREP machine\n");
>      }
> -    /* Hmm, prep has no pci-isa bridge ??? */
> -    isa_bus = isa_bus_new(NULL, get_system_io());
> -    i8259 = i8259_init(isa_bus, first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
>  
>      dev = qdev_create(NULL, "raven-pcihost");
>      sys = sysbus_from_qdev(dev);
> @@ -648,13 +617,21 @@ static void ppc_prep_init (ram_addr_t ram_size,
>          fprintf(stderr, "Couldn't create PCI host controller.\n");
>          exit(1);
>      }
> +
> +    /* PCI -> ISA bridge */
> +    pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
> +    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
> +    qdev_connect_gpio_out(&pci->qdev, 0,
> +                          first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
> +    qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
> +    isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
> +
> +    i8259 = isa_bus->irqs;

I think this is unneeded. You only access i8259[8] later on for
initializing the m48t59. But that one should be creatable as ISA device
now (m48t59_init_isa), no? Please check.

Jan

-- 
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux

Re: [Qemu-devel] [PATCH v3 8/8] prep: Use i82378 PCI->ISA bridge for 'prep' machine

[Andreas Färber]

Am 13.01.2012 10:21, schrieb Jan Kiszka:
> On 2012-01-13 04:09, Andreas Färber wrote:
>> +    isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
>> +
>> +    i8259 = isa_bus->irqs;
> 
> I think this is unneeded.

The problem here was that isa_get_irq() needs an ISADevice*, not just
the ISABus*, so I had to access ->irqs directly at this point.

Some of the later ISA devices are optional, others will be moved to the
pc87312. The i8042 might be an option if we really have to.

> You only access i8259[8] later on for
> initializing the m48t59.

And immediately following your quote i8259[9] and i8259[11] for the host
bridge.

The alternative would be to access the i8259's IRQs (initialized in the
PCI-ISA bridge needing the PCI host bridge) via a QOM property from
here. Or access the PCI host bridge from the PCI-ISA bridge init.

> But that one should be creatable as ISA device
> now (m48t59_init_isa), no? Please check.

Ah, that matches a patch by Hervé confusingly named "fix compilation".
Using the ISA version even resolves the m48t59 io_base issue I reported
earlier. I'll send a separate patch and rebase onto that.

Andreas

Re: [Qemu-devel] [PATCH v3 8/8] prep: Use i82378 PCI->ISA bridge for 'prep' machine

[Jan Kiszka]

On 2012-01-13 16:57, Andreas Färber wrote:
> Am 13.01.2012 10:21, schrieb Jan Kiszka:
>> On 2012-01-13 04:09, Andreas Färber wrote:
>>> +    isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
>>> +
>>> +    i8259 = isa_bus->irqs;
>>
>> I think this is unneeded.
> 
> The problem here was that isa_get_irq() needs an ISADevice*, not just
> the ISABus*, so I had to access ->irqs directly at this point.

Which is a hack that should not be merged.

> 
> Some of the later ISA devices are optional, others will be moved to the
> pc87312. The i8042 might be an option if we really have to.
> 
>> You only access i8259[8] later on for
>> initializing the m48t59.
> 
> And immediately following your quote i8259[9] and i8259[11] for the host
> bridge.

I was looking at upstream. Which patch is this?

> 
> The alternative would be to access the i8259's IRQs (initialized in the
> PCI-ISA bridge needing the PCI host bridge) via a QOM property from
> here. Or access the PCI host bridge from the PCI-ISA bridge init.
> 
>> But that one should be creatable as ISA device
>> now (m48t59_init_isa), no? Please check.
> 
> Ah, that matches a patch by Hervé confusingly named "fix compilation".
> Using the ISA version even resolves the m48t59 io_base issue I reported
> earlier. I'll send a separate patch and rebase onto that.

What about the other IRQs? Can they be associated with ISADevices as well?

Jan

-- 
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux

Re: [Qemu-devel] [PATCH v3 8/8] prep: Use i82378 PCI->ISA bridge for 'prep' machine

[Alexander Graf]

On 13.01.2012, at 17:08, Jan Kiszka wrote:

> On 2012-01-13 16:57, Andreas Färber wrote:
>> Am 13.01.2012 10:21, schrieb Jan Kiszka:
>>> On 2012-01-13 04:09, Andreas Färber wrote:
>>>> +    isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
>>>> +
>>>> +    i8259 = isa_bus->irqs;
>>> 
>>> I think this is unneeded.
>> 
>> The problem here was that isa_get_irq() needs an ISADevice*, not just
>> the ISABus*, so I had to access ->irqs directly at this point.
> 
> Which is a hack that should not be merged.
> 
>> 
>> Some of the later ISA devices are optional, others will be moved to the
>> pc87312. The i8042 might be an option if we really have to.
>> 
>>> You only access i8259[8] later on for
>>> initializing the m48t59.
>> 
>> And immediately following your quote i8259[9] and i8259[11] for the host
>> bridge.
> 
> I was looking at upstream. Which patch is this?

The patch you were commenting on :)

Alex

Re: [Qemu-devel] [PATCH v3 8/8] prep: Use i82378 PCI->ISA bridge for 'prep' machine

[Jan Kiszka]

On 2012-01-13 17:23, Alexander Graf wrote:
> 
> On 13.01.2012, at 17:08, Jan Kiszka wrote:
> 
>> On 2012-01-13 16:57, Andreas Färber wrote:
>>> Am 13.01.2012 10:21, schrieb Jan Kiszka:
>>>> On 2012-01-13 04:09, Andreas Färber wrote:
>>>>> +    isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
>>>>> +
>>>>> +    i8259 = isa_bus->irqs;
>>>>
>>>> I think this is unneeded.
>>>
>>> The problem here was that isa_get_irq() needs an ISADevice*, not just
>>> the ISABus*, so I had to access ->irqs directly at this point.
>>
>> Which is a hack that should not be merged.
>>
>>>
>>> Some of the later ISA devices are optional, others will be moved to the
>>> pc87312. The i8042 might be an option if we really have to.
>>>
>>>> You only access i8259[8] later on for
>>>> initializing the m48t59.
>>>
>>> And immediately following your quote i8259[9] and i8259[11] for the host
>>> bridge.
>>
>> I was looking at upstream. Which patch is this?
> 
> The patch you were commenting on :)

I see now. It just doesn't introduce it. :)

OK, so the problem is that the creator of the PIC does not export the
input IRQs in a way that they can be used by non-ISA chipset-external
devices as well. It's that fixable? Via GPIO pins of the chipset e.g.?

Jan

-- 
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux

Re: [Qemu-devel] [PATCH v3 0/8] qdev'ify PReP PCI host bridge and add PCI-to-ISA bridge

[Andreas Färber]

Am 13.01.2012 04:09, schrieb Andreas Färber:
> Hello,
> 
> Here's an updated initial qdev'ification series for PReP, as prerequisite
> for Anthony's second QOM series.

Available from
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/prep-queue
on top of all patches needed for testing.

> Andreas Färber (8):
>   prep: qdev'ify Raven host bridge (PCIDevice)
>   prep_pci: Simplify I/O endianness
>   prep_pci: Update I/O to MemoryRegion ops
>   prep: qdev'ify Raven host bridge (SysBus)
>   MAINTAINERS: Add PCI host bridge files to PReP machine
>   prep: Add i82374 DMA emulation
>   prep: Add i82378 PCI-to-ISA bridge emulation
>   prep: Use i82378 PCI->ISA bridge for 'prep' machine
> 
>  MAINTAINERS                     |    1 +
>  Makefile.objs                   |    2 +
>  default-configs/ppc-softmmu.mak |    3 +
>  hw/i82374.c                     |  154 ++++++++++++++++++++++++
>  hw/i82378.c                     |  252 +++++++++++++++++++++++++++++++++++++++
>  hw/pci_ids.h                    |    1 +
>  hw/ppc_prep.c                   |   77 +++++-------
>  hw/prep_pci.c                   |  181 +++++++++++++++++-----------
>  hw/prep_pci.h                   |   11 --
>  9 files changed, 553 insertions(+), 129 deletions(-)
>  create mode 100644 hw/i82374.c
>  create mode 100644 hw/i82378.c
>  delete mode 100644 hw/prep_pci.h

Re: [Qemu-devel] [PATCH v3 0/8] qdev'ify PReP PCI host bridge and add PCI-to-ISA bridge

[Alexander Graf]

On 13.01.2012, at 04:09, Andreas Färber wrote:

> Hello,
> 
> Here's an updated initial qdev'ification series for PReP, as prerequisite
> for Anthony's second QOM series.
> 
> As stated before, this is NOT a complete conversion of all PReP devices
> and of all those shared with x86. Please comment on what's there, not on
> what may be done, too. I'm sitting on these patches for over a year now,
> so let's start getting some of it merged so that we can move on with QOM
> and get some of the design issues fixed that kept the pc87312 Super I/O
> and 40P machine from getting merged in the first place!
> 
> Regards,
> Andreas

Looks good to me.

Reviewed-by: Alexander Graf <agraf@suse.de>


Alex

> 
> Changes since v2:
> * Simplify I/O byte swaps.
> * Convert I/O from old_mmio to MemoryRegion ops.
> * Drop pci_prep_init() and instantiate the PCI host bridge in the machine,
>  reintroducing PREPPCIState extension.
> * Connect IRQs via qdev after instantiating. Suggested by Alex.
> * Add a rebased PCI-to-ISA-bridge from the 40P series on top, to show why
>  some suggestions from v2 and IRC don't work out.
>  * Merge fix-up by Hervé: Add indirection for late-connected out[0] IRQ.
>  * Add VMState for i82374 and i82378.
>  * From i82378 drop the I/O address translation duplicated from the board.
>  * Rebase i82378 onto Memory API.
>  http://patchwork.ozlabs.org/patch/100250/
>  http://patchwork.ozlabs.org/patch/100272/
> * Add new patch from Hervé to wire up the PCI-to-ISA bridge for 'prep'.
> 
> Changes since v1:
> * Use the new .vendor_id etc. in PCIDeviceInfo
> * Rename from PRePPCI to Raven, adopt naming scheme from i440FX
> * Rebase onto multiple Memory API conversions
> * Split into PCIDevice and SysBus patches, leave out PREPPCIState changes
> http://patchwork.ozlabs.org/patch/100268/
> 
> Cc: Hervé Poussineau <hpoussin@reactos.org>
> Cc: Anthony Liguori <aliguori@us.ibm.com>
> Cc: Alexander Graf <agraf@suse.de>
> 
> Andreas Färber (8):
>  prep: qdev'ify Raven host bridge (PCIDevice)
>  prep_pci: Simplify I/O endianness
>  prep_pci: Update I/O to MemoryRegion ops
>  prep: qdev'ify Raven host bridge (SysBus)
>  MAINTAINERS: Add PCI host bridge files to PReP machine
>  prep: Add i82374 DMA emulation
>  prep: Add i82378 PCI-to-ISA bridge emulation
>  prep: Use i82378 PCI->ISA bridge for 'prep' machine
> 
> MAINTAINERS                     |    1 +
> Makefile.objs                   |    2 +
> default-configs/ppc-softmmu.mak |    3 +
> hw/i82374.c                     |  154 ++++++++++++++++++++++++
> hw/i82378.c                     |  252 +++++++++++++++++++++++++++++++++++++++
> hw/pci_ids.h                    |    1 +
> hw/ppc_prep.c                   |   77 +++++-------
> hw/prep_pci.c                   |  181 +++++++++++++++++-----------
> hw/prep_pci.h                   |   11 --
> 9 files changed, 553 insertions(+), 129 deletions(-)
> create mode 100644 hw/i82374.c
> create mode 100644 hw/i82378.c
> delete mode 100644 hw/prep_pci.h
> 
> -- 
> 1.7.7
> 

[Qemu-devel] [PATCH v4 0/8] qdev'ify PReP PCI host bridge and add PCI-to-ISA bridge

[Andreas Färber]

Hello,

Here's an improved initial qdev'ification series for PReP, as prerequisite
for Anthony's second QOM series.

On Jan's suggestion, the i8259 IRQs are exposed through qdev GPIO-in IRQs on
the i82378 PCI->ISA bridge

Regards,
Andreas

Changes since v3:
* i82378: Add i8259 IRQs as state and provide qdev GPIO-in access to them.
* prep: Update wiring of IRQs. Both suggested by Jan.

Changes since v2:
* Simplify I/O byte swaps.
* Convert I/O from old_mmio to MemoryRegion ops.
* Drop pci_prep_init() and instantiate the PCI host bridge in the machine,
  reintroducing PREPPCIState extension.
* Connect IRQs via qdev after instantiating. Suggested by Alex.
* Add a rebased PCI-to-ISA-bridge from the 40P series on top, to show why
  some suggestions from v2 and IRC don't work out.
  * Merge fix-up by Hervé: Add indirection for late-connected out[0] IRQ.
  * Add VMState for i82374 and i82378.
  * From i82378 drop the I/O address translation duplicated from the board.
  * Rebase i82378 onto Memory API.
  http://patchwork.ozlabs.org/patch/100250/
  http://patchwork.ozlabs.org/patch/100272/
* Add new patch from Hervé to wire up the PCI-to-ISA bridge for 'prep'.

Changes since v1:
* Use the new .vendor_id etc. in PCIDeviceInfo
* Rename from PRePPCI to Raven, adopt naming scheme from i440FX
* Rebase onto multiple Memory API conversions
* Split into PCIDevice and SysBus patches, leave out PREPPCIState changes
http://patchwork.ozlabs.org/patch/100268/

Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Anthony Liguori <aliguori@us.ibm.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Jan Kiszka <jan.kiszka@siemens.com>

Andreas Färber (8):
  prep: qdev'ify Raven host bridge (PCIDevice)
  prep_pci: Simplify I/O endianness
  prep_pci: Update I/O to MemoryRegion ops
  prep: qdev'ify Raven host bridge (SysBus)
  MAINTAINERS: Add PCI host bridge files to PReP machine
  prep: Add i82374 DMA emulation
  prep: Add i82378 PCI-to-ISA bridge emulation
  prep: Use i82378 PCI->ISA bridge for 'prep' machine

 MAINTAINERS                     |    1 +
 Makefile.objs                   |    2 +
 default-configs/ppc-softmmu.mak |    3 +
 hw/i82374.c                     |  154 +++++++++++++++++++++++
 hw/i82378.c                     |  264 +++++++++++++++++++++++++++++++++++++++
 hw/pci_ids.h                    |    1 +
 hw/ppc_prep.c                   |   76 +++++-------
 hw/prep_pci.c                   |  181 ++++++++++++++++-----------
 hw/prep_pci.h                   |   11 --
 9 files changed, 563 insertions(+), 130 deletions(-)
 create mode 100644 hw/i82374.c
 create mode 100644 hw/i82378.c
 delete mode 100644 hw/prep_pci.h

-- 
1.7.7

[Qemu-devel] [PATCH v4 1/8] prep: qdev'ify Raven host bridge (PCIDevice)

[Andreas Färber]

Move initialization of vendor ID, etc. to PCIDeviceInfo.
Introduce VMState.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>
---
 hw/prep_pci.c |   55 ++++++++++++++++++++++++++++++++++++++++++++++---------
 1 files changed, 46 insertions(+), 9 deletions(-)

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index ea9fb69..741b273 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -29,6 +29,10 @@
 
 typedef PCIHostState PREPPCIState;
 
+typedef struct RavenPCIState {
+    PCIDevice dev;
+} RavenPCIState;
+
 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
 {
     int i;
@@ -111,7 +115,6 @@ PCIBus *pci_prep_init(qemu_irq *pic,
                       MemoryRegion *address_space_io)
 {
     PREPPCIState *s;
-    PCIDevice *d;
 
     s = g_malloc0(sizeof(PREPPCIState));
     s->bus = pci_register_bus(NULL, "pci",
@@ -133,16 +136,50 @@ PCIBus *pci_prep_init(qemu_irq *pic,
     memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
     memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg);
 
-    /* PCI host bridge */
-    d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
-                            sizeof(PCIDevice), 0, NULL, NULL);
-    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
-    pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
-    d->config[0x08] = 0x00; // revision
-    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
+    pci_create_simple(s->bus, 0, "raven");
+
+    return s->bus;
+}
+
+static int raven_init(PCIDevice *d)
+{
     d->config[0x0C] = 0x08; // cache_line_size
     d->config[0x0D] = 0x10; // latency_timer
     d->config[0x34] = 0x00; // capabilities_pointer
 
-    return s->bus;
+    return 0;
 }
+
+static const VMStateDescription vmstate_raven = {
+    .name = "raven",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(dev, RavenPCIState),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static PCIDeviceInfo raven_info = {
+    .qdev.name = "raven",
+    .qdev.desc = "PReP Host Bridge - Motorola Raven",
+    .qdev.size = sizeof(RavenPCIState),
+    .qdev.vmsd = &vmstate_raven,
+    .qdev.no_user = 1,
+    .no_hotplug = 1,
+    .init = raven_init,
+    .vendor_id = PCI_VENDOR_ID_MOTOROLA,
+    .device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN,
+    .revision = 0x00,
+    .class_id = PCI_CLASS_BRIDGE_HOST,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_END_OF_LIST()
+    },
+};
+
+static void raven_register_devices(void)
+{
+    pci_qdev_register(&raven_info);
+}
+
+device_init(raven_register_devices)
-- 
1.7.7

[Qemu-devel] [PATCH v4 2/8] prep_pci: Simplify I/O endianness

[Andreas Färber]

The prep PowerPC CPU is Big Endian. An explicit byte swap therefore
effectively becomes Little Endian.

Remove explicit byte swaps and mark as Little Endian.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Cc: Michael S. Tsirkin <mst@redhat.com>
---
 hw/prep_pci.c |    6 +-----
 1 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 741b273..edfb25d 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -53,14 +53,12 @@ static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t va
 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     PREPPCIState *s = opaque;
-    val = bswap16(val);
     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
 }
 
 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
 {
     PREPPCIState *s = opaque;
-    val = bswap32(val);
     pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
 }
 
@@ -77,7 +75,6 @@ static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
     PREPPCIState *s = opaque;
     uint32_t val;
     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
-    val = bswap16(val);
     return val;
 }
 
@@ -86,7 +83,6 @@ static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
     PREPPCIState *s = opaque;
     uint32_t val;
     val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
-    val = bswap32(val);
     return val;
 }
 
@@ -95,7 +91,7 @@ static const MemoryRegionOps PPC_PCIIO_ops = {
         .read = { PPC_PCIIO_readb, PPC_PCIIO_readw, PPC_PCIIO_readl, },
         .write = { PPC_PCIIO_writeb, PPC_PCIIO_writew, PPC_PCIIO_writel, },
     },
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
-- 
1.7.7

[Qemu-devel] [PATCH v4 3/8] prep_pci: Update I/O to MemoryRegion ops

[Andreas Färber]

Convert to new-style read/write callbacks.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Benoît Canet <benoit.canet@gmail.com>
---
 hw/prep_pci.c |   61 +++++++++++++++++++++-----------------------------------
 1 files changed, 23 insertions(+), 38 deletions(-)

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index edfb25d..5970196 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -44,53 +44,38 @@ static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
     return (addr & 0x7ff) |  (i << 11);
 }
 
-static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
+static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
+                             uint64_t val, unsigned int size)
 {
     PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
-}
-
-static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
-}
-
-static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
-}
-
-static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
-{
-    PREPPCIState *s = opaque;
-    uint32_t val;
-    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
-    return val;
-}
-
-static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
-{
-    PREPPCIState *s = opaque;
-    uint32_t val;
-    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
-    return val;
+    switch (size) {
+    case 1:
+    case 2:
+    case 4:
+        pci_data_write(s->bus, PPC_PCIIO_config(addr), val, size);
+        break;
+    default:
+        abort();
+    }
 }
 
-static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
+static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
+                                unsigned int size)
 {
     PREPPCIState *s = opaque;
-    uint32_t val;
-    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
-    return val;
+    switch (size) {
+    case 1:
+    case 2:
+    case 4:
+        return pci_data_read(s->bus, PPC_PCIIO_config(addr), size);
+    default:
+        abort();
+    }
 }
 
 static const MemoryRegionOps PPC_PCIIO_ops = {
-    .old_mmio = {
-        .read = { PPC_PCIIO_readb, PPC_PCIIO_readw, PPC_PCIIO_readl, },
-        .write = { PPC_PCIIO_writeb, PPC_PCIIO_writew, PPC_PCIIO_writel, },
-    },
+    .read = ppc_pci_io_read,
+    .write = ppc_pci_io_write,
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-- 
1.7.7

[Qemu-devel] [PATCH v4 4/8] prep: qdev'ify Raven host bridge (SysBus)

[Andreas Färber]

Drop pci_prep_init() in favor of extended device state. Inspired by
patches from Hervé and Alex.

Assign the 4 IRQs from the board after device instantiation. This moves
the knowledge out of prep_pci and allows for future machines with
different IRQ wiring (IBM 40P). Suggested by Alex.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>
---
 hw/ppc_prep.c |   23 +++++++++++++++++-
 hw/prep_pci.c |   67 +++++++++++++++++++++++++++++++++++---------------------
 hw/prep_pci.h |   11 ---------
 3 files changed, 63 insertions(+), 38 deletions(-)
 delete mode 100644 hw/prep_pci.h

diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 1cc0ae0..62d0e36 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -29,7 +29,7 @@
 #include "sysemu.h"
 #include "isa.h"
 #include "pci.h"
-#include "prep_pci.h"
+#include "pci_host.h"
 #include "usb-ohci.h"
 #include "ppc.h"
 #include "boards.h"
@@ -522,6 +522,9 @@ static void ppc_prep_init (ram_addr_t ram_size,
     MemoryRegion *bios = g_new(MemoryRegion, 1);
     uint32_t kernel_base, initrd_base;
     long kernel_size, initrd_size;
+    DeviceState *dev;
+    SysBusDevice *sys;
+    PCIHostState *pcihost;
     PCIBus *pci_bus;
     ISABus *isa_bus;
     qemu_irq *i8259;
@@ -633,7 +636,23 @@ static void ppc_prep_init (ram_addr_t ram_size,
     /* Hmm, prep has no pci-isa bridge ??? */
     isa_bus = isa_bus_new(NULL, get_system_io());
     i8259 = i8259_init(isa_bus, first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
-    pci_bus = pci_prep_init(i8259, get_system_memory(), get_system_io());
+
+    dev = qdev_create(NULL, "raven-pcihost");
+    sys = sysbus_from_qdev(dev);
+    pcihost = DO_UPCAST(PCIHostState, busdev, sys);
+    pcihost->address_space = get_system_memory();
+    qdev_init_nofail(dev);
+    qdev_property_add_child(qdev_get_root(), "raven", dev, NULL);
+    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
+    if (pci_bus == NULL) {
+        fprintf(stderr, "Couldn't create PCI host controller.\n");
+        exit(1);
+    }
+    sysbus_connect_irq(&pcihost->busdev, 0, i8259[9]);
+    sysbus_connect_irq(&pcihost->busdev, 1, i8259[11]);
+    sysbus_connect_irq(&pcihost->busdev, 2, i8259[9]);
+    sysbus_connect_irq(&pcihost->busdev, 3, i8259[11]);
+
     isa_bus_irqs(isa_bus, i8259);
     //    pci_bus = i440fx_init();
     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 5970196..ccd0832 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -25,9 +25,12 @@
 #include "hw.h"
 #include "pci.h"
 #include "pci_host.h"
-#include "prep_pci.h"
+#include "exec-memory.h"
 
-typedef PCIHostState PREPPCIState;
+typedef struct PRePPCIState {
+    PCIHostState host_state;
+    qemu_irq irq[4];
+} PREPPCIState;
 
 typedef struct RavenPCIState {
     PCIDevice dev;
@@ -52,7 +55,7 @@ static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
     case 1:
     case 2:
     case 4:
-        pci_data_write(s->bus, PPC_PCIIO_config(addr), val, size);
+        pci_data_write(s->host_state.bus, PPC_PCIIO_config(addr), val, size);
         break;
     default:
         abort();
@@ -67,7 +70,7 @@ static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
     case 1:
     case 2:
     case 4:
-        return pci_data_read(s->bus, PPC_PCIIO_config(addr), size);
+        return pci_data_read(s->host_state.bus, PPC_PCIIO_config(addr), size);
     default:
         abort();
     }
@@ -88,38 +91,43 @@ static void prep_set_irq(void *opaque, int irq_num, int level)
 {
     qemu_irq *pic = opaque;
 
-    qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
+    qemu_set_irq(pic[irq_num] , level);
 }
 
-PCIBus *pci_prep_init(qemu_irq *pic,
-                      MemoryRegion *address_space_mem,
-                      MemoryRegion *address_space_io)
+static int raven_pcihost_init(SysBusDevice *dev)
 {
-    PREPPCIState *s;
+    PCIHostState *h = FROM_SYSBUS(PCIHostState, dev);
+    PREPPCIState *s = DO_UPCAST(PREPPCIState, host_state, h);
+    MemoryRegion *address_space_mem = get_system_memory();
+    MemoryRegion *address_space_io = get_system_io();
+    PCIBus *bus;
+    int i;
+
+    for (i = 0; i < 4; i++) {
+        sysbus_init_irq(dev, &s->irq[i]);
+    }
 
-    s = g_malloc0(sizeof(PREPPCIState));
-    s->bus = pci_register_bus(NULL, "pci",
-                              prep_set_irq, prep_map_irq, pic,
-                              address_space_mem,
-                              address_space_io,
-                              0, 4);
+    bus = pci_register_bus(&h->busdev.qdev, NULL,
+                           prep_set_irq, prep_map_irq, s->irq,
+                           address_space_mem, address_space_io, 0, 4);
+    h->bus = bus;
 
-    memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s,
+    memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, s,
                           "pci-conf-idx", 1);
-    memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
-    sysbus_init_ioports(&s->busdev, 0xcf8, 1);
+    sysbus_add_io(dev, 0xcf8, &h->conf_mem);
+    sysbus_init_ioports(&h->busdev, 0xcf8, 1);
 
-    memory_region_init_io(&s->data_mem, &pci_host_data_be_ops, s,
+    memory_region_init_io(&h->data_mem, &pci_host_data_be_ops, s,
                           "pci-conf-data", 1);
-    memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
-    sysbus_init_ioports(&s->busdev, 0xcfc, 1);
+    sysbus_add_io(dev, 0xcfc, &h->data_mem);
+    sysbus_init_ioports(&h->busdev, 0xcfc, 1);
 
-    memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
-    memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg);
+    memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
+    memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 
-    pci_create_simple(s->bus, 0, "raven");
+    pci_create_simple(bus, 0, "raven");
 
-    return s->bus;
+    return 0;
 }
 
 static int raven_init(PCIDevice *d)
@@ -158,8 +166,17 @@ static PCIDeviceInfo raven_info = {
     },
 };
 
+static SysBusDeviceInfo raven_pcihost_info = {
+    .qdev.name = "raven-pcihost",
+    .qdev.fw_name = "pci",
+    .qdev.size = sizeof(PREPPCIState),
+    .qdev.no_user = 1,
+    .init = raven_pcihost_init,
+};
+
 static void raven_register_devices(void)
 {
+    sysbus_register_withprop(&raven_pcihost_info);
     pci_qdev_register(&raven_info);
 }
 
diff --git a/hw/prep_pci.h b/hw/prep_pci.h
deleted file mode 100644
index b6b481a..0000000
--- a/hw/prep_pci.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef QEMU_PREP_PCI_H
-#define QEMU_PREP_PCI_H
-
-#include "qemu-common.h"
-#include "memory.h"
-
-PCIBus *pci_prep_init(qemu_irq *pic,
-                      MemoryRegion *address_space_mem,
-                      MemoryRegion *address_space_io);
-
-#endif
-- 
1.7.7

[Qemu-devel] [PATCH v4 5/8] MAINTAINERS: Add PCI host bridge files to PReP machine

[Andreas Färber]

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Acked-by: Alexander Graf <agraf@suse.de>
---
 MAINTAINERS |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index de2a916..148f0d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -307,6 +307,7 @@ PReP
 M: Andreas Färber <andreas.faerber@web.de>
 S: Odd Fixes
 F: hw/ppc_prep.c
+F: hw/prep_pci.[hc]
 
 SH4 Machines
 ------------
-- 
1.7.7

[Qemu-devel] [PATCH v4 6/8] prep: Add i82374 DMA emulation

[Andreas Färber]

Prepare Intel 82374 emulation for use by Intel 82378 PCI->ISA bridge.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Confine to CONFIG_I82374. Add VMState.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
 Makefile.objs                   |    1 +
 default-configs/ppc-softmmu.mak |    1 +
 hw/i82374.c                     |  154 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 156 insertions(+), 0 deletions(-)
 create mode 100644 hw/i82374.c

diff --git a/Makefile.objs b/Makefile.objs
index 4f6d26c..26af1f2 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -215,6 +215,7 @@ hw-obj-$(CONFIG_FDC) += fdc.o
 hw-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o
 hw-obj-$(CONFIG_APM) += pm_smbus.o apm.o
 hw-obj-$(CONFIG_DMA) += dma.o
+hw-obj-$(CONFIG_I82374) += i82374.o
 hw-obj-$(CONFIG_HPET) += hpet.o
 hw-obj-$(CONFIG_APPLESMC) += applesmc.o
 hw-obj-$(CONFIG_SMARTCARD) += usb-ccid.o ccid-card-passthru.o
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index c85cdce..e5905d5 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -11,6 +11,7 @@ CONFIG_I8254=y
 CONFIG_PCKBD=y
 CONFIG_FDC=y
 CONFIG_DMA=y
+CONFIG_I82374=y
 CONFIG_OPENPIC=y
 CONFIG_PREP_PCI=y
 CONFIG_MACIO=y
diff --git a/hw/i82374.c b/hw/i82374.c
new file mode 100644
index 0000000..616d1fc
--- /dev/null
+++ b/hw/i82374.c
@@ -0,0 +1,154 @@
+/*
+ * QEMU Intel 82374 emulation (Enhanced DMA controller)
+ *
+ * Copyright (c) 2010 Hervé Poussineau
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "isa.h"
+
+//#define DEBUG_I82374
+
+#ifdef DEBUG_I82374
+#define DPRINTF(fmt, ...) \
+do { fprintf(stderr, "i82374: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) \
+do {} while (0)
+#endif
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "i82374 ERROR: " fmt , ## __VA_ARGS__); } while (0)
+
+typedef struct I82374State {
+    uint8_t commands[8];
+} I82374State;
+
+static const VMStateDescription vmstate_i82374 = {
+    .name = "i82374",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8_ARRAY(commands, I82374State, 8),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static uint32_t i82374_read_isr(void *opaque, uint32_t nport)
+{
+    uint32_t val = 0;
+
+    BADF("%s: %08x\n", __func__, nport);
+
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
+    return val;
+}
+
+static void i82374_write_command(void *opaque, uint32_t nport, uint32_t data)
+{
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
+
+    if (data != 0x42) {
+        /* Not Stop S/G command */
+        BADF("%s: %08x=%08x\n", __func__, nport, data);
+    }
+}
+
+static uint32_t i82374_read_status(void *opaque, uint32_t nport)
+{
+    uint32_t val = 0;
+
+    BADF("%s: %08x\n", __func__, nport);
+
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
+    return val;
+}
+
+static void i82374_write_descriptor(void *opaque, uint32_t nport, uint32_t data)
+{
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
+
+    BADF("%s: %08x=%08x\n", __func__, nport, data);
+}
+
+static uint32_t i82374_read_descriptor(void *opaque, uint32_t nport)
+{
+    uint32_t val = 0;
+
+    BADF("%s: %08x\n", __func__, nport);
+
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
+    return val;
+}
+
+static void i82374_init(I82374State *s)
+{
+    DMA_init(1, NULL);
+    memset(s->commands, 0, sizeof(s->commands));
+}
+
+typedef struct ISAi82374State {
+    ISADevice dev;
+    uint32_t iobase;
+    I82374State state;
+} ISAi82374State;
+
+static const VMStateDescription vmstate_isa_i82374 = {
+    .name = "isa-i82374",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_STRUCT(state, ISAi82374State, 0, vmstate_i82374, I82374State),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static int i82374_isa_init(ISADevice *dev)
+{
+    ISAi82374State *isa = DO_UPCAST(ISAi82374State, dev, dev);
+    I82374State *s = &isa->state;
+
+    register_ioport_read(isa->iobase + 0x0A, 1, 1, i82374_read_isr, s);
+    register_ioport_write(isa->iobase + 0x10, 8, 1, i82374_write_command, s);
+    register_ioport_read(isa->iobase + 0x18, 8, 1, i82374_read_status, s);
+    register_ioport_write(isa->iobase + 0x20, 0x20, 1, i82374_write_descriptor, s);
+    register_ioport_read(isa->iobase + 0x20, 0x20, 1, i82374_read_descriptor, s);
+
+    i82374_init(s);
+
+    return 0;
+}
+
+static ISADeviceInfo i82374_isa_info = {
+    .qdev.name  = "i82374",
+    .qdev.size  = sizeof(ISAi82374State),
+    .qdev.vmsd  = &vmstate_isa_i82374,
+    .init       = i82374_isa_init,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_HEX32("iobase", ISAi82374State, iobase, 0x400),
+        DEFINE_PROP_END_OF_LIST()
+    },
+};
+
+static void i82374_register_devices(void)
+{
+    isa_qdev_register(&i82374_isa_info);
+}
+
+device_init(i82374_register_devices)
-- 
1.7.7

[Qemu-devel] [PATCH v4 7/8] prep: Add i82378 PCI-to-ISA bridge emulation

[Andreas Färber]

Prepare Intel 82378 emulation for use by PReP platforms.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Create ISA bus in this device (suggested by Markus).
Rebase onto Memory API, mark memory ops as Little Endian.
Add VMState. Provide access to i8259 IRQs via qdev GPIOs.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Markus Armbruster <armbru@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
---
 Makefile.objs                   |    1 +
 default-configs/ppc-softmmu.mak |    2 +
 hw/i82378.c                     |  264 +++++++++++++++++++++++++++++++++++++++
 hw/pci_ids.h                    |    1 +
 4 files changed, 268 insertions(+), 0 deletions(-)
 create mode 100644 hw/i82378.c

diff --git a/Makefile.objs b/Makefile.objs
index 26af1f2..656ae62 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -225,6 +225,7 @@ hw-obj-$(CONFIG_I8259) += i8259.o
 
 # PPC devices
 hw-obj-$(CONFIG_PREP_PCI) += prep_pci.o
+hw-obj-$(CONFIG_I82378) += i82378.o
 # Mac shared devices
 hw-obj-$(CONFIG_MACIO) += macio.o
 hw-obj-$(CONFIG_CUDA) += cuda.o
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index e5905d5..1fe9c6d 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -14,7 +14,9 @@ CONFIG_DMA=y
 CONFIG_I82374=y
 CONFIG_OPENPIC=y
 CONFIG_PREP_PCI=y
+CONFIG_I82378=y
 CONFIG_MACIO=y
+CONFIG_PCSPK=y
 CONFIG_CUDA=y
 CONFIG_ADB=y
 CONFIG_MAC_NVRAM=y
diff --git a/hw/i82378.c b/hw/i82378.c
new file mode 100644
index 0000000..95ae274
--- /dev/null
+++ b/hw/i82378.c
@@ -0,0 +1,264 @@
+/*
+ * QEMU Intel i82378 emulation (PCI to ISA bridge)
+ *
+ * Copyright (c) 2010-2011 Hervé Poussineau
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "pci.h"
+#include "pc.h"
+
+//#define DEBUG_I82378
+
+#ifdef DEBUG_I82378
+#define DPRINTF(fmt, ...) \
+do { fprintf(stderr, "i82378: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) \
+do {} while (0)
+#endif
+
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "i82378 ERROR: " fmt , ## __VA_ARGS__); } while (0)
+
+typedef struct I82378State {
+    qemu_irq out[2];
+    qemu_irq *i8259;
+    MemoryRegion io;
+    MemoryRegion mem;
+} I82378State;
+
+typedef struct PCIi82378State {
+    PCIDevice pci_dev;
+    uint32_t isa_io_base;
+    uint32_t isa_mem_base;
+    I82378State state;
+} PCIi82378State;
+
+static const VMStateDescription vmstate_pci_i82378 = {
+    .name = "pci-i82378",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(pci_dev, PCIi82378State),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static void i82378_io_write(void *opaque, target_phys_addr_t addr,
+                            uint64_t value, unsigned int size)
+{
+    switch (size) {
+    case 1:
+        DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outb(addr, value);
+        break;
+    case 2:
+        DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outw(addr, value);
+        break;
+    case 4:
+        DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outl(addr, value);
+        break;
+    default:
+        abort();
+    }
+}
+
+static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
+                               unsigned int size)
+{
+    DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
+    switch (size) {
+    case 1:
+        return cpu_inb(addr);
+    case 2:
+        return cpu_inw(addr);
+    case 4:
+        return cpu_inl(addr);
+    default:
+        abort();
+    }
+}
+
+static const MemoryRegionOps i82378_io_ops = {
+    .read = i82378_io_read,
+    .write = i82378_io_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
+                             uint64_t value, unsigned int size)
+{
+    switch (size) {
+    case 1:
+        DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outb(addr, value);
+        break;
+    case 2:
+        DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outw(addr, value);
+        break;
+    case 4:
+        DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outl(addr, value);
+        break;
+    default:
+        abort();
+    }
+}
+
+static uint64_t i82378_mem_read(void *opaque, target_phys_addr_t addr,
+                                unsigned int size)
+{
+    DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
+    switch (size) {
+    case 1:
+        return cpu_inb(addr);
+    case 2:
+        return cpu_inw(addr);
+    case 4:
+        return cpu_inl(addr);
+    default:
+        abort();
+    }
+}
+
+static const MemoryRegionOps i82378_mem_ops = {
+    .read = i82378_mem_read,
+    .write = i82378_mem_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void i82378_request_out0_irq(void *opaque, int irq, int level)
+{
+    I82378State *s = opaque;
+    qemu_set_irq(s->out[0], level);
+}
+
+static void i82378_request_pic_irq(void *opaque, int irq, int level)
+{
+    DeviceState *dev = opaque;
+    PCIDevice *pci = DO_UPCAST(PCIDevice, qdev, dev);
+    PCIi82378State *s = DO_UPCAST(PCIi82378State, pci_dev, pci);
+
+    qemu_set_irq(s->state.i8259[irq], level);
+}
+
+static void i82378_init(DeviceState *dev, I82378State *s)
+{
+    ISABus *isabus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(dev, "isa.0"));
+    ISADevice *pit;
+    qemu_irq *out0_irq;
+
+    /* This device has:
+       2 82C59 (irq)
+       1 82C54 (pit)
+       2 82C37 (dma)
+       NMI
+       Utility Bus Support Registers
+
+       All devices accept byte access only, except timer
+     */
+
+    qdev_init_gpio_out(dev, s->out, 2);
+    qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
+
+    /* Workaround the fact that i8259 is not qdev'ified... */
+    out0_irq = qemu_allocate_irqs(i82378_request_out0_irq, s, 1);
+
+    /* 2 82C59 (irq) */
+    s->i8259 = i8259_init(isabus, *out0_irq);
+    isa_bus_irqs(isabus, s->i8259);
+
+    /* 1 82C54 (pit) */
+    pit = pit_init(isabus, 0x40, 0);
+
+    /* speaker */
+    pcspk_init(pit);
+
+    /* 2 82C37 (dma) */
+    DMA_init(1, &s->out[1]);
+    isa_create_simple(isabus, "i82374");
+
+    /* timer */
+    isa_create_simple(isabus, "mc146818rtc");
+}
+
+static int pci_i82378_init(PCIDevice *dev)
+{
+    PCIi82378State *pci = DO_UPCAST(PCIi82378State, pci_dev, dev);
+    I82378State *s = &pci->state;
+    uint8_t *pci_conf;
+
+    pci_conf = dev->config;
+    pci_set_word(pci_conf + PCI_COMMAND,
+                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+    pci_set_word(pci_conf + PCI_STATUS,
+                 PCI_STATUS_DEVSEL_MEDIUM);
+
+    pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
+
+    memory_region_init_io(&s->io, &i82378_io_ops, s, "i82378-io", 0x00010000);
+    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io);
+
+    memory_region_init_io(&s->mem, &i82378_mem_ops, s, "i82378-mem", 0x01000000);
+    memory_region_set_coalescing(&s->mem);
+    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
+
+    /* Make I/O address read only */
+    pci_set_word(dev->wmask + PCI_COMMAND, PCI_COMMAND_SPECIAL);
+    pci_set_long(dev->wmask + PCI_BASE_ADDRESS_0, 0);
+    pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, pci->isa_io_base);
+
+    isa_mem_base = pci->isa_mem_base;
+    isa_bus_new(&dev->qdev, pci_address_space_io(dev));
+
+    i82378_init(&dev->qdev, s);
+
+    return 0;
+}
+
+static PCIDeviceInfo pci_i82378_info = {
+    .init = pci_i82378_init,
+    .qdev.name = "i82378",
+    .qdev.size = sizeof(PCIi82378State),
+    .qdev.vmsd = &vmstate_pci_i82378,
+    .vendor_id = PCI_VENDOR_ID_INTEL,
+    .device_id = PCI_DEVICE_ID_INTEL_82378,
+    .revision = 0x03,
+    .class_id = PCI_CLASS_BRIDGE_ISA,
+    .subsystem_vendor_id = 0x0,
+    .subsystem_id = 0x0,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_HEX32("iobase", PCIi82378State, isa_io_base, 0x80000000),
+        DEFINE_PROP_HEX32("membase", PCIi82378State, isa_mem_base, 0xc0000000),
+        DEFINE_PROP_END_OF_LIST()
+    },
+};
+
+static void i82378_register_devices(void)
+{
+    pci_qdev_register(&pci_i82378_info);
+}
+
+device_init(i82378_register_devices)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 83f3893..0fd643f 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -98,6 +98,7 @@
 #define PCI_DEVICE_ID_MPC8533E           0x0030
 
 #define PCI_VENDOR_ID_INTEL              0x8086
+#define PCI_DEVICE_ID_INTEL_82378        0x0484
 #define PCI_DEVICE_ID_INTEL_82441        0x1237
 #define PCI_DEVICE_ID_INTEL_82801AA_5    0x2415
 #define PCI_DEVICE_ID_INTEL_82801D       0x24CD
-- 
1.7.7

[Qemu-devel] [PATCH v4 8/8] prep: Use i82378 PCI->ISA bridge for 'prep' machine

[Andreas Färber]

Speaker I/O, ISA bus, i8259 PIC, RTC and DMA are no longer set up
individually by the machine. Effectively, no-op speaker I/O is replaced
by pcspk; PIT and i82374 DMA are introduced.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Remove related dead, alternative code.
Wire up PCI host bridge IRQs via GPIO-in IRQs of PCI->ISA bridge.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Alexander Graf <agraf@suse.de>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
---
 hw/ppc_prep.c |   61 ++++++++++++--------------------------------------------
 1 files changed, 13 insertions(+), 48 deletions(-)

diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 62d0e36..438a75d 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -83,37 +83,9 @@ static const int ide_irq[2] = { 13, 13 };
 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 
-//static ISADevice *pit;
-
 /* ISA IO ports bridge */
 #define PPC_IO_BASE 0x80000000
 
-#if 0
-/* Speaker port 0x61 */
-static int speaker_data_on;
-static int dummy_refresh_clock;
-#endif
-
-static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
-{
-#if 0
-    speaker_data_on = (val >> 1) & 1;
-    pit_set_gate(pit, 2, val & 1);
-#endif
-}
-
-static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
-{
-#if 0
-    int out;
-    out = pit_get_out(pit, 2, qemu_get_clock_ns(vm_clock));
-    dummy_refresh_clock ^= 1;
-    return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
-        (dummy_refresh_clock << 4);
-#endif
-    return 0;
-}
-
 /* PCI intack register */
 /* Read-only register (?) */
 static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
@@ -526,8 +498,8 @@ static void ppc_prep_init (ram_addr_t ram_size,
     SysBusDevice *sys;
     PCIHostState *pcihost;
     PCIBus *pci_bus;
+    PCIDevice *pci;
     ISABus *isa_bus;
-    qemu_irq *i8259;
     qemu_irq *cpu_exit_irq;
     int ppc_boot_device;
     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
@@ -629,13 +601,9 @@ static void ppc_prep_init (ram_addr_t ram_size,
         }
     }
 
-    isa_mem_base = 0xc0000000;
     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
         hw_error("Only 6xx bus is supported on PREP machine\n");
     }
-    /* Hmm, prep has no pci-isa bridge ??? */
-    isa_bus = isa_bus_new(NULL, get_system_io());
-    i8259 = i8259_init(isa_bus, first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 
     dev = qdev_create(NULL, "raven-pcihost");
     sys = sysbus_from_qdev(dev);
@@ -648,13 +616,19 @@ static void ppc_prep_init (ram_addr_t ram_size,
         fprintf(stderr, "Couldn't create PCI host controller.\n");
         exit(1);
     }
-    sysbus_connect_irq(&pcihost->busdev, 0, i8259[9]);
-    sysbus_connect_irq(&pcihost->busdev, 1, i8259[11]);
-    sysbus_connect_irq(&pcihost->busdev, 2, i8259[9]);
-    sysbus_connect_irq(&pcihost->busdev, 3, i8259[11]);
 
-    isa_bus_irqs(isa_bus, i8259);
-    //    pci_bus = i440fx_init();
+    /* PCI -> ISA bridge */
+    pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
+    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
+    qdev_connect_gpio_out(&pci->qdev, 0,
+                          first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
+    qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
+    sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
+    sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
+    sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
+    sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
+    isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
+
     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
     memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
                           "ppc-io", 0x00800000);
@@ -662,9 +636,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
 
     /* init basic PC hardware */
     pci_vga_init(pci_bus);
-    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
-    //    pit = pit_init(0x40, 0);
-    rtc_init(isa_bus, 2000, NULL);
 
     if (serial_hds[0])
         serial_isa_init(isa_bus, 0, serial_hds[0]);
@@ -691,9 +662,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
     }
     isa_create_simple(isa_bus, "i8042");
 
-    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
-    DMA_init(1, cpu_exit_irq);
-
     //    SB16_init();
 
     for(i = 0; i < MAX_FD; i++) {
@@ -701,9 +669,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
     }
     fdctrl_init_isa(isa_bus, fd);
 
-    /* Register speaker port */
-    register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
-    register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
     /* Register fake IO ports for PREP */
     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
-- 
1.7.7

Re: [Qemu-devel] [PATCH v4 0/8] qdev'ify PReP PCI host bridge and add PCI-to-ISA bridge

[Andreas Färber]

Am 13.01.2012 20:03, schrieb Andreas Färber:
> Andreas Färber (8):
>   prep: qdev'ify Raven host bridge (PCIDevice)
>   prep_pci: Simplify I/O endianness

Applied 1-2 to prep-up branch:
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/prep-up

/-F

>   prep_pci: Update I/O to MemoryRegion ops
>   prep: qdev'ify Raven host bridge (SysBus)
>   MAINTAINERS: Add PCI host bridge files to PReP machine
>   prep: Add i82374 DMA emulation
>   prep: Add i82378 PCI-to-ISA bridge emulation
>   prep: Use i82378 PCI->ISA bridge for 'prep' machine

[Qemu-devel] [PATCH v5 0/6] qdev'ify PReP PCI host bridge and add PCI-to-ISA bridge

[Andreas Färber]

Hello,

Here's a slightly simplified qdev'ification series for PReP.

Sizes other than 1/2/4 are currently not supported, so no need to abort().

Regards,
Andreas

Changes since v4:
* Patches 1-2 were applied to prep-up, thus drop.
* Drop switch statements for prep_pci_io_{read,write}(). Suggested by Avi.

Changes since v3:
* i82378: Add i8259 IRQs as state and provide qdev GPIO-in access to them.
* prep: Update wiring of IRQs. Both suggested by Jan.

Changes since v2:
* Simplify I/O byte swaps.
* Convert I/O from old_mmio to MemoryRegion ops.
* Drop pci_prep_init() and instantiate the PCI host bridge in the machine,
  reintroducing PREPPCIState extension.
* Connect IRQs via qdev after instantiating. Suggested by Alex.
* Add a rebased PCI-to-ISA-bridge from the 40P series on top, to show why
  some suggestions from v2 and IRC don't work out.
  * Merge fix-up by Hervé: Add indirection for late-connected out[0] IRQ.
  * Add VMState for i82374 and i82378.
  * From i82378 drop the I/O address translation duplicated from the board.
  * Rebase i82378 onto Memory API.
  http://patchwork.ozlabs.org/patch/100250/
  http://patchwork.ozlabs.org/patch/100272/
* Add new patch from Hervé to wire up the PCI-to-ISA bridge for 'prep'.

Changes since v1:
* Use the new .vendor_id etc. in PCIDeviceInfo
* Rename from PRePPCI to Raven, adopt naming scheme from i440FX
* Rebase onto multiple Memory API conversions
* Split into PCIDevice and SysBus patches, leave out PREPPCIState changes
http://patchwork.ozlabs.org/patch/100268/

Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Anthony Liguori <aliguori@us.ibm.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Jan Kiszka <jan.kiszka@siemens.com>

Andreas Färber (6):
  prep_pci: Update I/O to MemoryRegion ops
  prep: qdev'ify Raven host bridge (SysBus)
  MAINTAINERS: Add PCI host bridge files to PReP machine
  prep: Add i82374 DMA emulation
  prep: Add i82378 PCI-to-ISA bridge emulation
  prep: Use i82378 PCI->ISA bridge for 'prep' machine

 MAINTAINERS                     |    1 +
 Makefile.objs                   |    2 +
 default-configs/ppc-softmmu.mak |    3 +
 hw/i82374.c                     |  154 +++++++++++++++++++++++
 hw/i82378.c                     |  264 +++++++++++++++++++++++++++++++++++++++
 hw/pci_ids.h                    |    1 +
 hw/ppc_prep.c                   |   76 +++++-------
 hw/prep_pci.c                   |  109 +++++++---------
 hw/prep_pci.h                   |   11 --
 9 files changed, 503 insertions(+), 118 deletions(-)
 create mode 100644 hw/i82374.c
 create mode 100644 hw/i82378.c
 delete mode 100644 hw/prep_pci.h

-- 
1.7.7

[Qemu-devel] [PATCH v5 1/6] prep_pci: Update I/O to MemoryRegion ops

[Andreas Färber]

Convert to new-style read/write callbacks.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Alexander Graf <agraf@suse.de>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Avi Kivity <avi@redhat.com>
Cc: Benoît Canet <benoit.canet@gmail.com>
---
 hw/prep_pci.c |   46 ++++++++--------------------------------------
 1 files changed, 8 insertions(+), 38 deletions(-)

diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index edfb25d..2600e26 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -44,53 +44,23 @@ static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
     return (addr & 0x7ff) |  (i << 11);
 }
 
-static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
+static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
+                             uint64_t val, unsigned int size)
 {
     PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
+    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, size);
 }
 
-static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
+static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
+                                unsigned int size)
 {
     PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
-}
-
-static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
-    PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
-}
-
-static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
-{
-    PREPPCIState *s = opaque;
-    uint32_t val;
-    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
-    return val;
-}
-
-static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
-{
-    PREPPCIState *s = opaque;
-    uint32_t val;
-    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
-    return val;
-}
-
-static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
-{
-    PREPPCIState *s = opaque;
-    uint32_t val;
-    val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
-    return val;
+    return pci_data_read(s->bus, PPC_PCIIO_config(addr), size);
 }
 
 static const MemoryRegionOps PPC_PCIIO_ops = {
-    .old_mmio = {
-        .read = { PPC_PCIIO_readb, PPC_PCIIO_readw, PPC_PCIIO_readl, },
-        .write = { PPC_PCIIO_writeb, PPC_PCIIO_writew, PPC_PCIIO_writel, },
-    },
+    .read = ppc_pci_io_read,
+    .write = ppc_pci_io_write,
     .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
-- 
1.7.7

[Qemu-devel] [PATCH v5 2/6] prep: qdev'ify Raven host bridge (SysBus)

[Andreas Färber]

Drop pci_prep_init() in favor of extended device state. Inspired by
patches from Hervé and Alex.

Assign the 4 IRQs from the board after device instantiation. This moves
the knowledge out of prep_pci and allows for future machines with
different IRQ wiring (IBM 40P). Suggested by Alex.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
Cc: Hervé Poussineau <hpoussin@reactos.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Anthony Liguori <aliguori@us.ibm.com>
---
 hw/ppc_prep.c |   23 +++++++++++++++++-
 hw/prep_pci.c |   67 +++++++++++++++++++++++++++++++++++---------------------
 hw/prep_pci.h |   11 ---------
 3 files changed, 63 insertions(+), 38 deletions(-)
 delete mode 100644 hw/prep_pci.h

diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 1cc0ae0..62d0e36 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -29,7 +29,7 @@
 #include "sysemu.h"
 #include "isa.h"
 #include "pci.h"
-#include "prep_pci.h"
+#include "pci_host.h"
 #include "usb-ohci.h"
 #include "ppc.h"
 #include "boards.h"
@@ -522,6 +522,9 @@ static void ppc_prep_init (ram_addr_t ram_size,
     MemoryRegion *bios = g_new(MemoryRegion, 1);
     uint32_t kernel_base, initrd_base;
     long kernel_size, initrd_size;
+    DeviceState *dev;
+    SysBusDevice *sys;
+    PCIHostState *pcihost;
     PCIBus *pci_bus;
     ISABus *isa_bus;
     qemu_irq *i8259;
@@ -633,7 +636,23 @@ static void ppc_prep_init (ram_addr_t ram_size,
     /* Hmm, prep has no pci-isa bridge ??? */
     isa_bus = isa_bus_new(NULL, get_system_io());
     i8259 = i8259_init(isa_bus, first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
-    pci_bus = pci_prep_init(i8259, get_system_memory(), get_system_io());
+
+    dev = qdev_create(NULL, "raven-pcihost");
+    sys = sysbus_from_qdev(dev);
+    pcihost = DO_UPCAST(PCIHostState, busdev, sys);
+    pcihost->address_space = get_system_memory();
+    qdev_init_nofail(dev);
+    qdev_property_add_child(qdev_get_root(), "raven", dev, NULL);
+    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
+    if (pci_bus == NULL) {
+        fprintf(stderr, "Couldn't create PCI host controller.\n");
+        exit(1);
+    }
+    sysbus_connect_irq(&pcihost->busdev, 0, i8259[9]);
+    sysbus_connect_irq(&pcihost->busdev, 1, i8259[11]);
+    sysbus_connect_irq(&pcihost->busdev, 2, i8259[9]);
+    sysbus_connect_irq(&pcihost->busdev, 3, i8259[11]);
+
     isa_bus_irqs(isa_bus, i8259);
     //    pci_bus = i440fx_init();
     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 2600e26..4961eed 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -25,9 +25,12 @@
 #include "hw.h"
 #include "pci.h"
 #include "pci_host.h"
-#include "prep_pci.h"
+#include "exec-memory.h"
 
-typedef PCIHostState PREPPCIState;
+typedef struct PRePPCIState {
+    PCIHostState host_state;
+    qemu_irq irq[4];
+} PREPPCIState;
 
 typedef struct RavenPCIState {
     PCIDevice dev;
@@ -48,14 +51,14 @@ static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
                              uint64_t val, unsigned int size)
 {
     PREPPCIState *s = opaque;
-    pci_data_write(s->bus, PPC_PCIIO_config(addr), val, size);
+    pci_data_write(s->host_state.bus, PPC_PCIIO_config(addr), val, size);
 }
 
 static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
                                 unsigned int size)
 {
     PREPPCIState *s = opaque;
-    return pci_data_read(s->bus, PPC_PCIIO_config(addr), size);
+    return pci_data_read(s->host_state.bus, PPC_PCIIO_config(addr), size);
 }
 
 static const MemoryRegionOps PPC_PCIIO_ops = {
@@ -73,38 +76,43 @@ static void prep_set_irq(void *opaque, int irq_num, int level)
 {
     qemu_irq *pic = opaque;
 
-    qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
+    qemu_set_irq(pic[irq_num] , level);
 }
 
-PCIBus *pci_prep_init(qemu_irq *pic,
-                      MemoryRegion *address_space_mem,
-                      MemoryRegion *address_space_io)
+static int raven_pcihost_init(SysBusDevice *dev)
 {
-    PREPPCIState *s;
+    PCIHostState *h = FROM_SYSBUS(PCIHostState, dev);
+    PREPPCIState *s = DO_UPCAST(PREPPCIState, host_state, h);
+    MemoryRegion *address_space_mem = get_system_memory();
+    MemoryRegion *address_space_io = get_system_io();
+    PCIBus *bus;
+    int i;
+
+    for (i = 0; i < 4; i++) {
+        sysbus_init_irq(dev, &s->irq[i]);
+    }
 
-    s = g_malloc0(sizeof(PREPPCIState));
-    s->bus = pci_register_bus(NULL, "pci",
-                              prep_set_irq, prep_map_irq, pic,
-                              address_space_mem,
-                              address_space_io,
-                              0, 4);
+    bus = pci_register_bus(&h->busdev.qdev, NULL,
+                           prep_set_irq, prep_map_irq, s->irq,
+                           address_space_mem, address_space_io, 0, 4);
+    h->bus = bus;
 
-    memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s,
+    memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, s,
                           "pci-conf-idx", 1);
-    memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
-    sysbus_init_ioports(&s->busdev, 0xcf8, 1);
+    sysbus_add_io(dev, 0xcf8, &h->conf_mem);
+    sysbus_init_ioports(&h->busdev, 0xcf8, 1);
 
-    memory_region_init_io(&s->data_mem, &pci_host_data_be_ops, s,
+    memory_region_init_io(&h->data_mem, &pci_host_data_be_ops, s,
                           "pci-conf-data", 1);
-    memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
-    sysbus_init_ioports(&s->busdev, 0xcfc, 1);
+    sysbus_add_io(dev, 0xcfc, &h->data_mem);
+    sysbus_init_ioports(&h->busdev, 0xcfc, 1);
 
-    memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
-    memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg);
+    memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
+    memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 
-    pci_create_simple(s->bus, 0, "raven");
+    pci_create_simple(bus, 0, "raven");
 
-    return s->bus;
+    return 0;
 }
 
 static int raven_init(PCIDevice *d)
@@ -143,8 +151,17 @@ static PCIDeviceInfo raven_info = {
     },
 };
 
+static SysBusDeviceInfo raven_pcihost_info = {
+    .qdev.name = "raven-pcihost",
+    .qdev.fw_name = "pci",
+    .qdev.size = sizeof(PREPPCIState),
+    .qdev.no_user = 1,
+    .init = raven_pcihost_init,
+};
+
 static void raven_register_devices(void)
 {
+    sysbus_register_withprop(&raven_pcihost_info);
     pci_qdev_register(&raven_info);
 }
 
diff --git a/hw/prep_pci.h b/hw/prep_pci.h
deleted file mode 100644
index b6b481a..0000000
--- a/hw/prep_pci.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef QEMU_PREP_PCI_H
-#define QEMU_PREP_PCI_H
-
-#include "qemu-common.h"
-#include "memory.h"
-
-PCIBus *pci_prep_init(qemu_irq *pic,
-                      MemoryRegion *address_space_mem,
-                      MemoryRegion *address_space_io);
-
-#endif
-- 
1.7.7

[Qemu-devel] [PATCH v5 3/6] MAINTAINERS: Add PCI host bridge files to PReP machine

[Andreas Färber]

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Acked-by: Alexander Graf <agraf@suse.de>
---
 MAINTAINERS |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index de2a916..148f0d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -307,6 +307,7 @@ PReP
 M: Andreas Färber <andreas.faerber@web.de>
 S: Odd Fixes
 F: hw/ppc_prep.c
+F: hw/prep_pci.[hc]
 
 SH4 Machines
 ------------
-- 
1.7.7

[Qemu-devel] [PATCH v5 4/6] prep: Add i82374 DMA emulation

[Andreas Färber]

Prepare Intel 82374 emulation for use by Intel 82378 PCI->ISA bridge.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Confine to CONFIG_I82374. Add VMState.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Reviewed-by: Alexander Graf <agraf@suse.de>
---
 Makefile.objs                   |    1 +
 default-configs/ppc-softmmu.mak |    1 +
 hw/i82374.c                     |  154 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 156 insertions(+), 0 deletions(-)
 create mode 100644 hw/i82374.c

diff --git a/Makefile.objs b/Makefile.objs
index 4f6d26c..26af1f2 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -215,6 +215,7 @@ hw-obj-$(CONFIG_FDC) += fdc.o
 hw-obj-$(CONFIG_ACPI) += acpi.o acpi_piix4.o
 hw-obj-$(CONFIG_APM) += pm_smbus.o apm.o
 hw-obj-$(CONFIG_DMA) += dma.o
+hw-obj-$(CONFIG_I82374) += i82374.o
 hw-obj-$(CONFIG_HPET) += hpet.o
 hw-obj-$(CONFIG_APPLESMC) += applesmc.o
 hw-obj-$(CONFIG_SMARTCARD) += usb-ccid.o ccid-card-passthru.o
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index c85cdce..e5905d5 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -11,6 +11,7 @@ CONFIG_I8254=y
 CONFIG_PCKBD=y
 CONFIG_FDC=y
 CONFIG_DMA=y
+CONFIG_I82374=y
 CONFIG_OPENPIC=y
 CONFIG_PREP_PCI=y
 CONFIG_MACIO=y
diff --git a/hw/i82374.c b/hw/i82374.c
new file mode 100644
index 0000000..616d1fc
--- /dev/null
+++ b/hw/i82374.c
@@ -0,0 +1,154 @@
+/*
+ * QEMU Intel 82374 emulation (Enhanced DMA controller)
+ *
+ * Copyright (c) 2010 Hervé Poussineau
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "isa.h"
+
+//#define DEBUG_I82374
+
+#ifdef DEBUG_I82374
+#define DPRINTF(fmt, ...) \
+do { fprintf(stderr, "i82374: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) \
+do {} while (0)
+#endif
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "i82374 ERROR: " fmt , ## __VA_ARGS__); } while (0)
+
+typedef struct I82374State {
+    uint8_t commands[8];
+} I82374State;
+
+static const VMStateDescription vmstate_i82374 = {
+    .name = "i82374",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8_ARRAY(commands, I82374State, 8),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static uint32_t i82374_read_isr(void *opaque, uint32_t nport)
+{
+    uint32_t val = 0;
+
+    BADF("%s: %08x\n", __func__, nport);
+
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
+    return val;
+}
+
+static void i82374_write_command(void *opaque, uint32_t nport, uint32_t data)
+{
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
+
+    if (data != 0x42) {
+        /* Not Stop S/G command */
+        BADF("%s: %08x=%08x\n", __func__, nport, data);
+    }
+}
+
+static uint32_t i82374_read_status(void *opaque, uint32_t nport)
+{
+    uint32_t val = 0;
+
+    BADF("%s: %08x\n", __func__, nport);
+
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
+    return val;
+}
+
+static void i82374_write_descriptor(void *opaque, uint32_t nport, uint32_t data)
+{
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, data);
+
+    BADF("%s: %08x=%08x\n", __func__, nport, data);
+}
+
+static uint32_t i82374_read_descriptor(void *opaque, uint32_t nport)
+{
+    uint32_t val = 0;
+
+    BADF("%s: %08x\n", __func__, nport);
+
+    DPRINTF("%s: %08x=%08x\n", __func__, nport, val);
+    return val;
+}
+
+static void i82374_init(I82374State *s)
+{
+    DMA_init(1, NULL);
+    memset(s->commands, 0, sizeof(s->commands));
+}
+
+typedef struct ISAi82374State {
+    ISADevice dev;
+    uint32_t iobase;
+    I82374State state;
+} ISAi82374State;
+
+static const VMStateDescription vmstate_isa_i82374 = {
+    .name = "isa-i82374",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_STRUCT(state, ISAi82374State, 0, vmstate_i82374, I82374State),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static int i82374_isa_init(ISADevice *dev)
+{
+    ISAi82374State *isa = DO_UPCAST(ISAi82374State, dev, dev);
+    I82374State *s = &isa->state;
+
+    register_ioport_read(isa->iobase + 0x0A, 1, 1, i82374_read_isr, s);
+    register_ioport_write(isa->iobase + 0x10, 8, 1, i82374_write_command, s);
+    register_ioport_read(isa->iobase + 0x18, 8, 1, i82374_read_status, s);
+    register_ioport_write(isa->iobase + 0x20, 0x20, 1, i82374_write_descriptor, s);
+    register_ioport_read(isa->iobase + 0x20, 0x20, 1, i82374_read_descriptor, s);
+
+    i82374_init(s);
+
+    return 0;
+}
+
+static ISADeviceInfo i82374_isa_info = {
+    .qdev.name  = "i82374",
+    .qdev.size  = sizeof(ISAi82374State),
+    .qdev.vmsd  = &vmstate_isa_i82374,
+    .init       = i82374_isa_init,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_HEX32("iobase", ISAi82374State, iobase, 0x400),
+        DEFINE_PROP_END_OF_LIST()
+    },
+};
+
+static void i82374_register_devices(void)
+{
+    isa_qdev_register(&i82374_isa_info);
+}
+
+device_init(i82374_register_devices)
-- 
1.7.7

[Qemu-devel] [PATCH v5 5/6] prep: Add i82378 PCI-to-ISA bridge emulation

[Andreas Färber]

Prepare Intel 82378 emulation for use by PReP platforms.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Create ISA bus in this device (suggested by Markus).
Rebase onto Memory API, mark memory ops as Little Endian.
Add VMState. Provide access to i8259 IRQs via qdev GPIOs.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Markus Armbruster <armbru@redhat.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
---
 Makefile.objs                   |    1 +
 default-configs/ppc-softmmu.mak |    2 +
 hw/i82378.c                     |  264 +++++++++++++++++++++++++++++++++++++++
 hw/pci_ids.h                    |    1 +
 4 files changed, 268 insertions(+), 0 deletions(-)
 create mode 100644 hw/i82378.c

diff --git a/Makefile.objs b/Makefile.objs
index 26af1f2..656ae62 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -225,6 +225,7 @@ hw-obj-$(CONFIG_I8259) += i8259.o
 
 # PPC devices
 hw-obj-$(CONFIG_PREP_PCI) += prep_pci.o
+hw-obj-$(CONFIG_I82378) += i82378.o
 # Mac shared devices
 hw-obj-$(CONFIG_MACIO) += macio.o
 hw-obj-$(CONFIG_CUDA) += cuda.o
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index e5905d5..1fe9c6d 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -14,7 +14,9 @@ CONFIG_DMA=y
 CONFIG_I82374=y
 CONFIG_OPENPIC=y
 CONFIG_PREP_PCI=y
+CONFIG_I82378=y
 CONFIG_MACIO=y
+CONFIG_PCSPK=y
 CONFIG_CUDA=y
 CONFIG_ADB=y
 CONFIG_MAC_NVRAM=y
diff --git a/hw/i82378.c b/hw/i82378.c
new file mode 100644
index 0000000..95ae274
--- /dev/null
+++ b/hw/i82378.c
@@ -0,0 +1,264 @@
+/*
+ * QEMU Intel i82378 emulation (PCI to ISA bridge)
+ *
+ * Copyright (c) 2010-2011 Hervé Poussineau
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "pci.h"
+#include "pc.h"
+
+//#define DEBUG_I82378
+
+#ifdef DEBUG_I82378
+#define DPRINTF(fmt, ...) \
+do { fprintf(stderr, "i82378: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) \
+do {} while (0)
+#endif
+
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "i82378 ERROR: " fmt , ## __VA_ARGS__); } while (0)
+
+typedef struct I82378State {
+    qemu_irq out[2];
+    qemu_irq *i8259;
+    MemoryRegion io;
+    MemoryRegion mem;
+} I82378State;
+
+typedef struct PCIi82378State {
+    PCIDevice pci_dev;
+    uint32_t isa_io_base;
+    uint32_t isa_mem_base;
+    I82378State state;
+} PCIi82378State;
+
+static const VMStateDescription vmstate_pci_i82378 = {
+    .name = "pci-i82378",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_PCI_DEVICE(pci_dev, PCIi82378State),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static void i82378_io_write(void *opaque, target_phys_addr_t addr,
+                            uint64_t value, unsigned int size)
+{
+    switch (size) {
+    case 1:
+        DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outb(addr, value);
+        break;
+    case 2:
+        DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outw(addr, value);
+        break;
+    case 4:
+        DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outl(addr, value);
+        break;
+    default:
+        abort();
+    }
+}
+
+static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
+                               unsigned int size)
+{
+    DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
+    switch (size) {
+    case 1:
+        return cpu_inb(addr);
+    case 2:
+        return cpu_inw(addr);
+    case 4:
+        return cpu_inl(addr);
+    default:
+        abort();
+    }
+}
+
+static const MemoryRegionOps i82378_io_ops = {
+    .read = i82378_io_read,
+    .write = i82378_io_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
+                             uint64_t value, unsigned int size)
+{
+    switch (size) {
+    case 1:
+        DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outb(addr, value);
+        break;
+    case 2:
+        DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outw(addr, value);
+        break;
+    case 4:
+        DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
+                addr, value);
+        cpu_outl(addr, value);
+        break;
+    default:
+        abort();
+    }
+}
+
+static uint64_t i82378_mem_read(void *opaque, target_phys_addr_t addr,
+                                unsigned int size)
+{
+    DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
+    switch (size) {
+    case 1:
+        return cpu_inb(addr);
+    case 2:
+        return cpu_inw(addr);
+    case 4:
+        return cpu_inl(addr);
+    default:
+        abort();
+    }
+}
+
+static const MemoryRegionOps i82378_mem_ops = {
+    .read = i82378_mem_read,
+    .write = i82378_mem_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void i82378_request_out0_irq(void *opaque, int irq, int level)
+{
+    I82378State *s = opaque;
+    qemu_set_irq(s->out[0], level);
+}
+
+static void i82378_request_pic_irq(void *opaque, int irq, int level)
+{
+    DeviceState *dev = opaque;
+    PCIDevice *pci = DO_UPCAST(PCIDevice, qdev, dev);
+    PCIi82378State *s = DO_UPCAST(PCIi82378State, pci_dev, pci);
+
+    qemu_set_irq(s->state.i8259[irq], level);
+}
+
+static void i82378_init(DeviceState *dev, I82378State *s)
+{
+    ISABus *isabus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(dev, "isa.0"));
+    ISADevice *pit;
+    qemu_irq *out0_irq;
+
+    /* This device has:
+       2 82C59 (irq)
+       1 82C54 (pit)
+       2 82C37 (dma)
+       NMI
+       Utility Bus Support Registers
+
+       All devices accept byte access only, except timer
+     */
+
+    qdev_init_gpio_out(dev, s->out, 2);
+    qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
+
+    /* Workaround the fact that i8259 is not qdev'ified... */
+    out0_irq = qemu_allocate_irqs(i82378_request_out0_irq, s, 1);
+
+    /* 2 82C59 (irq) */
+    s->i8259 = i8259_init(isabus, *out0_irq);
+    isa_bus_irqs(isabus, s->i8259);
+
+    /* 1 82C54 (pit) */
+    pit = pit_init(isabus, 0x40, 0);
+
+    /* speaker */
+    pcspk_init(pit);
+
+    /* 2 82C37 (dma) */
+    DMA_init(1, &s->out[1]);
+    isa_create_simple(isabus, "i82374");
+
+    /* timer */
+    isa_create_simple(isabus, "mc146818rtc");
+}
+
+static int pci_i82378_init(PCIDevice *dev)
+{
+    PCIi82378State *pci = DO_UPCAST(PCIi82378State, pci_dev, dev);
+    I82378State *s = &pci->state;
+    uint8_t *pci_conf;
+
+    pci_conf = dev->config;
+    pci_set_word(pci_conf + PCI_COMMAND,
+                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+    pci_set_word(pci_conf + PCI_STATUS,
+                 PCI_STATUS_DEVSEL_MEDIUM);
+
+    pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
+
+    memory_region_init_io(&s->io, &i82378_io_ops, s, "i82378-io", 0x00010000);
+    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io);
+
+    memory_region_init_io(&s->mem, &i82378_mem_ops, s, "i82378-mem", 0x01000000);
+    memory_region_set_coalescing(&s->mem);
+    pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
+
+    /* Make I/O address read only */
+    pci_set_word(dev->wmask + PCI_COMMAND, PCI_COMMAND_SPECIAL);
+    pci_set_long(dev->wmask + PCI_BASE_ADDRESS_0, 0);
+    pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, pci->isa_io_base);
+
+    isa_mem_base = pci->isa_mem_base;
+    isa_bus_new(&dev->qdev, pci_address_space_io(dev));
+
+    i82378_init(&dev->qdev, s);
+
+    return 0;
+}
+
+static PCIDeviceInfo pci_i82378_info = {
+    .init = pci_i82378_init,
+    .qdev.name = "i82378",
+    .qdev.size = sizeof(PCIi82378State),
+    .qdev.vmsd = &vmstate_pci_i82378,
+    .vendor_id = PCI_VENDOR_ID_INTEL,
+    .device_id = PCI_DEVICE_ID_INTEL_82378,
+    .revision = 0x03,
+    .class_id = PCI_CLASS_BRIDGE_ISA,
+    .subsystem_vendor_id = 0x0,
+    .subsystem_id = 0x0,
+    .qdev.props = (Property[]) {
+        DEFINE_PROP_HEX32("iobase", PCIi82378State, isa_io_base, 0x80000000),
+        DEFINE_PROP_HEX32("membase", PCIi82378State, isa_mem_base, 0xc0000000),
+        DEFINE_PROP_END_OF_LIST()
+    },
+};
+
+static void i82378_register_devices(void)
+{
+    pci_qdev_register(&pci_i82378_info);
+}
+
+device_init(i82378_register_devices)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 83f3893..0fd643f 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -98,6 +98,7 @@
 #define PCI_DEVICE_ID_MPC8533E           0x0030
 
 #define PCI_VENDOR_ID_INTEL              0x8086
+#define PCI_DEVICE_ID_INTEL_82378        0x0484
 #define PCI_DEVICE_ID_INTEL_82441        0x1237
 #define PCI_DEVICE_ID_INTEL_82801AA_5    0x2415
 #define PCI_DEVICE_ID_INTEL_82801D       0x24CD
-- 
1.7.7

[Qemu-devel] [PATCH v5 6/6] prep: Use i82378 PCI->ISA bridge for 'prep' machine

[Andreas Färber]

Speaker I/O, ISA bus, i8259 PIC, RTC and DMA are no longer set up
individually by the machine. Effectively, no-op speaker I/O is replaced
by pcspk; PIT and i82374 DMA are introduced.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

Remove related dead, alternative code.
Wire up PCI host bridge IRQs via GPIO-in IRQs of PCI->ISA bridge.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
Cc: Alexander Graf <agraf@suse.de>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
---
 hw/ppc_prep.c |   61 ++++++++++++--------------------------------------------
 1 files changed, 13 insertions(+), 48 deletions(-)

diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 62d0e36..438a75d 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -83,37 +83,9 @@ static const int ide_irq[2] = { 13, 13 };
 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 
-//static ISADevice *pit;
-
 /* ISA IO ports bridge */
 #define PPC_IO_BASE 0x80000000
 
-#if 0
-/* Speaker port 0x61 */
-static int speaker_data_on;
-static int dummy_refresh_clock;
-#endif
-
-static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
-{
-#if 0
-    speaker_data_on = (val >> 1) & 1;
-    pit_set_gate(pit, 2, val & 1);
-#endif
-}
-
-static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
-{
-#if 0
-    int out;
-    out = pit_get_out(pit, 2, qemu_get_clock_ns(vm_clock));
-    dummy_refresh_clock ^= 1;
-    return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
-        (dummy_refresh_clock << 4);
-#endif
-    return 0;
-}
-
 /* PCI intack register */
 /* Read-only register (?) */
 static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
@@ -526,8 +498,8 @@ static void ppc_prep_init (ram_addr_t ram_size,
     SysBusDevice *sys;
     PCIHostState *pcihost;
     PCIBus *pci_bus;
+    PCIDevice *pci;
     ISABus *isa_bus;
-    qemu_irq *i8259;
     qemu_irq *cpu_exit_irq;
     int ppc_boot_device;
     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
@@ -629,13 +601,9 @@ static void ppc_prep_init (ram_addr_t ram_size,
         }
     }
 
-    isa_mem_base = 0xc0000000;
     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
         hw_error("Only 6xx bus is supported on PREP machine\n");
     }
-    /* Hmm, prep has no pci-isa bridge ??? */
-    isa_bus = isa_bus_new(NULL, get_system_io());
-    i8259 = i8259_init(isa_bus, first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 
     dev = qdev_create(NULL, "raven-pcihost");
     sys = sysbus_from_qdev(dev);
@@ -648,13 +616,19 @@ static void ppc_prep_init (ram_addr_t ram_size,
         fprintf(stderr, "Couldn't create PCI host controller.\n");
         exit(1);
     }
-    sysbus_connect_irq(&pcihost->busdev, 0, i8259[9]);
-    sysbus_connect_irq(&pcihost->busdev, 1, i8259[11]);
-    sysbus_connect_irq(&pcihost->busdev, 2, i8259[9]);
-    sysbus_connect_irq(&pcihost->busdev, 3, i8259[11]);
 
-    isa_bus_irqs(isa_bus, i8259);
-    //    pci_bus = i440fx_init();
+    /* PCI -> ISA bridge */
+    pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
+    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
+    qdev_connect_gpio_out(&pci->qdev, 0,
+                          first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
+    qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
+    sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
+    sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
+    sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
+    sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
+    isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
+
     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
     memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
                           "ppc-io", 0x00800000);
@@ -662,9 +636,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
 
     /* init basic PC hardware */
     pci_vga_init(pci_bus);
-    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
-    //    pit = pit_init(0x40, 0);
-    rtc_init(isa_bus, 2000, NULL);
 
     if (serial_hds[0])
         serial_isa_init(isa_bus, 0, serial_hds[0]);
@@ -691,9 +662,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
     }
     isa_create_simple(isa_bus, "i8042");
 
-    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
-    DMA_init(1, cpu_exit_irq);
-
     //    SB16_init();
 
     for(i = 0; i < MAX_FD; i++) {
@@ -701,9 +669,6 @@ static void ppc_prep_init (ram_addr_t ram_size,
     }
     fdctrl_init_isa(isa_bus, fd);
 
-    /* Register speaker port */
-    register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
-    register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
     /* Register fake IO ports for PREP */
     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
-- 
1.7.7

Re: [Qemu-devel] [PATCH v5 0/6] qdev'ify PReP PCI host bridge and add PCI-to-ISA bridge

[Andreas Färber]

Am 16.01.2012 17:18, schrieb Andreas Färber:
> Andreas Färber (6):
>   prep_pci: Update I/O to MemoryRegion ops
>   prep: qdev'ify Raven host bridge (SysBus)
>   MAINTAINERS: Add PCI host bridge files to PReP machine
>   prep: Add i82374 DMA emulation
>   prep: Add i82378 PCI-to-ISA bridge emulation
>   prep: Use i82378 PCI->ISA bridge for 'prep' machine

All applied to the prep-up branch:
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/prep-up

Andreas