From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([140.186.70.92]:40164)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <mark.langsdorf@calxeda.com>) id 1RnaqL-0007Eu-Kx
	for qemu-devel@nongnu.org; Wed, 18 Jan 2012 14:06:46 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <mark.langsdorf@calxeda.com>) id 1RnaqH-00084D-Bw
	for qemu-devel@nongnu.org; Wed, 18 Jan 2012 14:06:45 -0500
Received: from smtp201.dfw.emailsrvr.com ([67.192.241.201]:38200)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <mark.langsdorf@calxeda.com>) id 1RnaqH-000845-56
	for qemu-devel@nongnu.org; Wed, 18 Jan 2012 14:06:41 -0500
Message-ID: <4F171842.7070000@calxeda.com>
Date: Wed, 18 Jan 2012 13:06:42 -0600
From: Mark Langsdorf <mark.langsdorf@calxeda.com>
MIME-Version: 1.0
References: <1326213943-878-1-git-send-email-mark.langsdorf@calxeda.com>
	<1326808231-32545-1-git-send-email-mark.langsdorf@calxeda.com>
	<1326808231-32545-5-git-send-email-mark.langsdorf@calxeda.com>
	<CAFEAcA9D3DSTet3Py_4rPc1mGiS8NQNwJ7tnZF2UT1VWiSW3qQ@mail.gmail.com>
	<4F16D8AA.6020307@calxeda.com>
	<CAFEAcA-WOvr5mDpWR5d-x10MtC6wWOHhnbUTsniVwNwTZ9GaPQ@mail.gmail.com>
In-Reply-To: <CAFEAcA-WOvr5mDpWR5d-x10MtC6wWOHhnbUTsniVwNwTZ9GaPQ@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH v10 4/5] arm: SoC model for Calxeda Highbank
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "i.mitsyanko@gmail.com" <i.mitsyanko@gmail.com>, "edgar.iglesias@gmail.com" <edgar.iglesias@gmail.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, Rob Herring <rob.herring@calxeda.com>, "afaerber@suse.de" <afaerber@suse.de>

On 01/18/2012 08:53 AM, Peter Maydell wrote:
> On 18 January 2012 14:35, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
>> I can set the smp_loader code so that I can boot 2 cpus
>> and verify their existence in /proc/cpuinfo, but I can't
>> get 3 cpus to boot at all, no matter how I hack the existing
>> arm_boot code.
> 
> Right, multiple secondary cores requires multiple addresses
> to be polled which we don't support in arm_boot.c at the moment.

How would multiple polling supposed to work? I've tried changing
http://lxr.linux.no/#linux+v3.2.1/arch/arm/mach-highbank/highbank.c#L71
to point to a fixed address (0x50), and the boot loader still fails
if there are 2 or more secondary CPUs.

I've figured out that do_cpu_reset() is only called once, even
though that seems a bit strange to me. I've tried the following
in my local secondary_hook call:

    switch (info->nb_cpus) {
    case 4:
        stl_phys_notdirty(0x70, 0);
    case 3:
        stl_phys_notdirty(0x60, 0);
    case 2:
        stl_phys_notdirty(0x50, 0);
        env->regs[15] = 0x100;
        break;
    }

which works fine with 2 cpus, but fails to boot both
secondary cpus if there are 3 total cpus.

--Mark Langsdorf
Calxeda, Inc.