From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:48990) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RoLGD-00029A-CN for qemu-devel@nongnu.org; Fri, 20 Jan 2012 15:40:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RoLGC-0001dj-FK for qemu-devel@nongnu.org; Fri, 20 Jan 2012 15:40:33 -0500 Message-ID: <4F19D131.7000800@freescale.com> Date: Fri, 20 Jan 2012 14:40:17 -0600 From: Scott Wood MIME-Version: 1.0 References: <1327029449-13220-1-git-send-email-agraf@suse.de> <1327029449-13220-7-git-send-email-agraf@suse.de> In-Reply-To: <1327029449-13220-7-git-send-email-agraf@suse.de> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 6/6] PPC: booke206: Implement tlbilx List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: qemu-ppc@nongnu.org, qemu-devel Developers On 01/19/2012 09:17 PM, Alexander Graf wrote: > + case 3: > + /* flush by pid and ea */ > + for (i = 0; i < BOOKE206_MAX_TLBN; i++) { > + int ways = booke206_tlb_ways(env, i); > + > + for (j = 0; j < ways; j++) { > + tlb = booke206_get_tlbm(env, i, address, j); > + if ((ppcmas_tlb_check(env, tlb, NULL, address, pid) != 0) || > + (tlb->mas1 & MAS1_IPROT) || > + ((tlb->mas1 & MAS1_TS) != ts) || > + ((tlb->mas1 & MAS1_IND) != ind) || > + ((tlb->mas1 & MAS1_TSIZE_MASK) != size) || > + ((tlb->mas8 & MAS8_TGS) != sgs)) { > + continue; > + } > + tlb->mas1 &= ~MAS1_VALID; > + } ISIZE is only supported on MAV=2.0, and then only if TLB write conditional or Hardware Entry Select is supported. Also, I don't know to what extent you want to emulate particular cores versus a generic implementation of the architecture, but e500mc does not filter on MAS6[SAS]. This is permitted as noted in 6.7.1's Programming Note allowing generous TLB invalidations, and is documented this way in the e500mc manual so software could be relying on it. -Scott