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From: Scott Wood <scottwood@freescale.com>
To: Alexander Graf <agraf@suse.de>
Cc: "<qemu-ppc@nongnu.org>" <qemu-ppc@nongnu.org>,
	qemu-devel Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 7/8] PPC: booke206: Check for min/max TLB entry size
Date: Mon, 23 Jan 2012 15:41:01 -0600	[thread overview]
Message-ID: <4F1DD3ED.50101@freescale.com> (raw)
In-Reply-To: <353F52B3-BC7E-471B-BB8A-9DA6C06C2A59@suse.de>

On 01/23/2012 03:29 PM, Alexander Graf wrote:
> 
> 
> On 23.01.2012, at 21:10, Scott Wood <scottwood@freescale.com> wrote:
> 
>> If TLB0 has TLBnCFG[AVAIL] set, then with this patch you'll be raising
>> an exception rather than setting the size to the minimum.
>>
>> If TLB0 does not have TLBnCFG[AVAIL] set, you'll be letting the user set
>> whatever size they want.
>>
>> In either case, you seem to be letting the user write whatever the want
>> to the TLB array, and only afterward check whether to send an exception.
> 
> Yes, for !AVAIL we simply override the page size on qemu tlb miss iirc.

Ah.  That seems like a hotter path than tlbwe, and you could still
insert an invalid entry into tlb1 (you'd get an exception, but the entry
would be there).

> Is that wrong? Does tlbwe;tlbre result in different tsize values?

e500mc manual (table 6-6, "MMU Assist Register Field Updates") says
tlbre returns a tsize of 1 for tlb0 -- it doesn't store tsize.  The KVM
MMU API also requires that tsize be stored as a valid value, to simplify
the code that operates on the TLB.  The TLB dump code depends on this
(could be fixed of course, but simpler to fix it once in tlbwe).

>>> True. Maybe we should just always reserve a surplus TLB entry and have the current code work, basically making it be a nop?
>>>
>>> Or we could add checks everywhere...
>>
>> I'd have booke206_get_tlbm() check and return NULL, with callers
>> checking for that.  Optimization can come later, if/when it's shown to
>> be a bottleneck.
> 
> It's more about not missing any cases :). But yeah, it's probably best to just change the semantics.

At least a NULL deference will be more noticeable than an array overrun...

-Scott

  reply	other threads:[~2012-01-23 21:41 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-01-21  4:15 [Qemu-devel] [PATCH 0/8] Make -cpu e500mc useful in TCG v2 Alexander Graf
2012-01-21  4:15 ` [Qemu-devel] [PATCH 1/8] PPC: Add IVOR 38-42 Alexander Graf
2012-01-21  4:15 ` [Qemu-devel] [PATCH 2/8] PPC: e500mc: add missing IVORs to bitmap Alexander Graf
2012-01-21  4:15 ` [Qemu-devel] [PATCH 3/8] PPC: e500: msync is 440 only, e500 has real sync Alexander Graf
2012-01-21  4:15 ` [Qemu-devel] [PATCH 4/8] PPC: rename msync to msync_4xx Alexander Graf
2012-01-21  4:15 ` [Qemu-devel] [PATCH 5/8] PPC: booke206: allow NULL raddr in ppcmas_tlb_check Alexander Graf
2012-01-21  4:15 ` [Qemu-devel] [PATCH 6/8] PPC: booke: add tlbnps handling Alexander Graf
2012-01-23 17:29   ` Scott Wood
2012-01-23 17:33     ` Alexander Graf
2012-01-21  4:15 ` [Qemu-devel] [PATCH 7/8] PPC: booke206: Check for min/max TLB entry size Alexander Graf
2012-01-23 17:32   ` Scott Wood
2012-01-23 17:33     ` Alexander Graf
2012-01-23 18:19       ` Scott Wood
2012-01-23 18:41         ` Alexander Graf
2012-01-23 18:49           ` Scott Wood
2012-01-23 20:03             ` Alexander Graf
2012-01-23 20:10               ` Scott Wood
2012-01-23 21:29                 ` Alexander Graf
2012-01-23 21:41                   ` Scott Wood [this message]
2012-01-21  4:15 ` [Qemu-devel] [PATCH 8/8] PPC: booke206: Implement tlbilx Alexander Graf
2012-01-21 20:04   ` Blue Swirl
2012-01-23 16:49     ` [Qemu-devel] [PATCH] " Alexander Graf

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