From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:51678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RpbJz-0006hH-VC for qemu-devel@nongnu.org; Tue, 24 Jan 2012 03:01:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RpbJt-0003Za-RQ for qemu-devel@nongnu.org; Tue, 24 Jan 2012 03:01:39 -0500 Received: from cantor2.suse.de ([195.135.220.15]:59261 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RpbJt-0003ZV-Gp for qemu-devel@nongnu.org; Tue, 24 Jan 2012 03:01:33 -0500 Message-ID: <4F1E64DC.3000302@suse.de> Date: Tue, 24 Jan 2012 08:59:24 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1326487969-12462-1-git-send-email-peter.maydell@linaro.org> <1326487969-12462-11-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1326487969-12462-11-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 10/12] Add Cortex-A15 CPU definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, android-virt@lists.cs.columbia.edu, patches@linaro.org Am 13.01.2012 21:52, schrieb Peter Maydell: > Add a definition of a Cortex-A15 CPU. Note that for the moment we do > not implement any of: > * Large Physical Address Extensions (LPAE) > * Virtualization Extensions > * Generic Timer > * TrustZone (this is also true of our existing Cortex-A9 model, etc) >=20 > This CPU model is sufficient to boot a Linux kernel which has been > compiled for an A15 without LPAE enabled. >=20 > Signed-off-by: Peter Maydell > --- > target-arm/cpu.h | 1 + > target-arm/helper.c | 56 +++++++++++++++++++++++++++++++++++++++++++= +++---- > 2 files changed, 52 insertions(+), 5 deletions(-) >=20 > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index d5403ea..4b8d680 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -433,6 +433,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, > #define ARM_CPUID_CORTEXA8 0x410fc080 > #define ARM_CPUID_CORTEXA9 0x410fc090 > #define ARM_CPUID_CORTEXM3 0x410fc231 > +#define ARM_CPUID_CORTEXA15 0x412fc0f1 Reminder of our rnpn topic... We don't seem to have a clear ordering system but I'd suggest to move A15 one line up, to group the As and Ms in ascending order respectively. > #define ARM_CPUID_ANY 0xffffffff > =20 > #if defined(CONFIG_USER_ONLY) > diff --git a/target-arm/helper.c b/target-arm/helper.c > index de4a50f..a68dc5c 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -10,6 +10,16 @@ > #if !defined(CONFIG_USER_ONLY) > #include "hw/loader.h" > #endif > +#include "sysemu.h" > + > +static uint32_t cortexa15_cp15_c0_c1[8] =3D { > + 0x00001131, 0x00011011, 0x02010555, 0x00000000, > + 0x10201105, 0x20000000, 0x01240000, 0x02102211 > +}; > + > +static uint32_t cortexa15_cp15_c0_c2[8] =3D { > + 0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, = 0 > +}; > =20 > static uint32_t cortexa9_cp15_c0_c1[8] =3D > { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x000021= 11 }; > @@ -158,6 +168,27 @@ static void cpu_reset_model_id(CPUARMState *env, u= int32_t id) > env->cp15.c0_ccsid[1] =3D 0x200fe015; /* 16k L1 icache. */ > env->cp15.c1_sys =3D 0x00c50078; > break; > + case ARM_CPUID_CORTEXA15: > + set_feature(env, ARM_FEATURE_V7); > + set_feature(env, ARM_FEATURE_VFP4); > + set_feature(env, ARM_FEATURE_VFP_FP16); > + set_feature(env, ARM_FEATURE_NEON); > + set_feature(env, ARM_FEATURE_THUMB2EE); > + set_feature(env, ARM_FEATURE_ARM_DIV); > + set_feature(env, ARM_FEATURE_V7MP); > + set_feature(env, ARM_FEATURE_GENERICTIMER); Features look sane. > @@ -413,6 +444,7 @@ static const struct arm_cpu_t arm_cpu_names[] =3D { > { ARM_CPUID_CORTEXM3, "cortex-m3"}, > { ARM_CPUID_CORTEXA8, "cortex-a8"}, > { ARM_CPUID_CORTEXA9, "cortex-a9"}, > + { ARM_CPUID_CORTEXA15, "cortex-a15"}, Space please. > { ARM_CPUID_TI925T, "ti925t" }, > { ARM_CPUID_PXA250, "pxa250" }, > { ARM_CPUID_SA1100, "sa1100" }, > @@ -667,8 +699,6 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint= 32_t mode) > =20 > #else > =20 > -extern int semihosting_enabled; > - > /* Map CPU modes onto saved register banks. */ > static inline int bank_number(CPUState *env, int mode) > { > @@ -1934,6 +1964,7 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t= insn) > case ARM_CPUID_CORTEXA8: > return 2; > case ARM_CPUID_CORTEXA9: > + case ARM_CPUID_CORTEXA15: > return 0; > default: > goto bad_reg; > @@ -2054,11 +2085,26 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32= _t insn) > goto bad_reg; > } > case 1: /* L2 cache */ > - if (crm !=3D 0) { > + /* L2 Lockdown and Auxiliary control. */ > + switch (op2) { > + case 0: > + /* L2 cache lockdown (A8 only) */ > + return 0; > + case 2: > + /* L2 cache auxiliary control (A8) or control (A15= ) */ > + if (ARM_CPUID(env) =3D=3D ARM_CPUID_CORTEXA15) { Change of mind? You opposed uses of ARM_CPUID() for Cortex-R4F. Andreas > + /* Linux wants the number of processors from h= ere. > + * Might as well set the interrupt-controller = bit too. > + */ > + return ((smp_cpus - 1) << 24) | (1 << 23); > + } > + return 0; > + case 3: > + /* L2 cache extended control (A15) */ > + return 0; > + default: > goto bad_reg; > } > - /* L2 Lockdown and Auxiliary control. */ > - return 0; > default: > goto bad_reg; > } --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg