From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:38455) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rq22b-0007In-T6 for qemu-devel@nongnu.org; Wed, 25 Jan 2012 07:33:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rq22a-0002pf-Da for qemu-devel@nongnu.org; Wed, 25 Jan 2012 07:33:29 -0500 Received: from cantor2.suse.de ([195.135.220.15]:57973 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rq22a-0002pb-7b for qemu-devel@nongnu.org; Wed, 25 Jan 2012 07:33:28 -0500 Message-ID: <4F1FF617.1090404@suse.de> Date: Wed, 25 Jan 2012 13:31:19 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1327408760-3666-1-git-send-email-peter.maydell@linaro.org> <1327408760-3666-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1327408760-3666-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 2/9] Add Cortex-A15 CPU definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org Am 24.01.2012 13:39, schrieb Peter Maydell: > Add a definition of a Cortex-A15 CPU. Note that for the moment we do > not implement any of: > * Large Physical Address Extensions (LPAE) > * Virtualization Extensions > * Generic Timer > * TrustZone (this is also true of our existing Cortex-A9 model, etc) >=20 > This CPU model is sufficient to boot a Linux kernel which has been > compiled for an A15 without LPAE enabled. >=20 > Signed-off-by: Peter Maydell Reviewed-by: Andreas F=E4rber Thanks, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg