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[77.13.123.197]) by smtp.gmail.com with ESMTPSA id h26-20020a170906829a00b00965c529f103sm5512101ejx.86.2023.06.12.12.25.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Jun 2023 12:25:21 -0700 (PDT) Date: Mon, 12 Jun 2023 17:49:10 +0000 From: Bernhard Beschow To: Igor Mammedov CC: qemu-devel@nongnu.org, "Michael S. Tsirkin" , Paolo Bonzini , Richard Henderson , Marcel Apfelbaum , Eduardo Habkost Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_15/15=5D_hw/i386/pc=5Fpiix=3A_Mo?= =?US-ASCII?Q?ve_i440fx=27_realize_near_its_qdev=5Fnew=28=29?= In-Reply-To: <20230612172119.5b9e6d7e@imammedo.users.ipa.redhat.com> References: <20230611103412.12109-1-shentey@gmail.com> <20230611103412.12109-16-shentey@gmail.com> <20230612165155.087ba275@imammedo.users.ipa.redhat.com> <20230612172119.5b9e6d7e@imammedo.users.ipa.redhat.com> Message-ID: <4F200210-F39C-49CD-B7FD-AF9F556C8493@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 12=2E Juni 2023 15:21:19 UTC schrieb Igor Mammedov : >On Mon, 12 Jun 2023 16:51:55 +0200 >Igor Mammedov wrote: > >> On Sun, 11 Jun 2023 12:34:12 +0200 >> Bernhard Beschow wrote: >>=20 >> > I440FX realization is currently mixed with PIIX3 creation=2E Furtherm= ore, it is >> > common practice to only set properties between a device's qdev_new() = and >> > qdev_realize()=2E Clean up to resolve both issues=2E >> >=20 >> > Since I440FX spawns a PCI bus let's also move the pci_bus initializat= ion there=2E >> >=20 >> > Note that when running `qemu-system-x86_64 -M pc -S` before and after= this >> > patch, `info mtree` in the QEMU console doesn't show any differences = except that >> > the ordering is different=2E >> >=20 >> > Signed-off-by: Bernhard Beschow >> > --- >> > hw/i386/pc_piix=2Ec | 57 ++++++++++++++++++++++++-------------------= ---- >> > 1 file changed, 29 insertions(+), 28 deletions(-) >> >=20 >> > diff --git a/hw/i386/pc_piix=2Ec b/hw/i386/pc_piix=2Ec >> > index 22173b122b=2E=2E23b9725c94 100644 >> > --- a/hw/i386/pc_piix=2Ec >> > +++ b/hw/i386/pc_piix=2Ec >> > @@ -126,7 +126,6 @@ static void pc_init1(MachineState *machine, >> > MemoryRegion *rom_memory; >> > ram_addr_t lowmem; >> > uint64_t hole64_size; >> > - Object *i440fx_host; >> > =20 >> > /* >> > * Calculate ram split, for memory below and above 4G=2E It's a= bit >> > @@ -198,17 +197,43 @@ static void pc_init1(MachineState *machine, >> > } >> > =20 >> > if (pcmc->pci_enabled) { >> > + Object *phb; >> > + >> > pci_memory =3D g_new(MemoryRegion, 1); >> > memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); >> > rom_memory =3D pci_memory; >> > - i440fx_host =3D OBJECT(qdev_new(host_type)); >> > - hole64_size =3D object_property_get_uint(i440fx_host, >> > + >> > + phb =3D OBJECT(qdev_new(host_type)); >> > + object_property_add_child(OBJECT(machine), "i440fx", phb); >> > + object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, >> > + OBJECT(ram_memory), &error_fatal); >> > + object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, >> > + OBJECT(pci_memory), &error_fatal); >> > + object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, >> > + OBJECT(system_memory), &error_fatal= ); >> > + object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, >> > + OBJECT(system_io), &error_fatal); >> > + object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE, >> > + x86ms->below_4g_mem_size, &error_fa= tal); >> > + object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, >> > + x86ms->above_4g_mem_size, &error_fa= tal); >> > + object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_= type, >> > + &error_fatal); >> > + sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); >> > + >> > + pci_bus =3D PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci=2E0= ")); >> > + pci_bus_map_irqs(pci_bus, >> > + xen_enabled() ? xen_pci_slot_get_pirq >> > + : pc_pci_slot_get_pirq); >> > + pcms->bus =3D pci_bus; >> > + >> > + hole64_size =3D object_property_get_uint(phb, >> > PCI_HOST_PROP_PCI_HOL= E64_SIZE, >> > &error_abort); =20 >>=20 >> before patch memory region links were set after the original >> regions were initialized by pc_memory_init(), but after this >> patch you 1st set links and only later pc_memory_init()=2E >> I doesn't look to me as a safe thing to do=2E > >or maybe it doesn't matter, but still I have hard time >convincing myself that it is so=2E=20 AFAICS both pc_memory_init() and i440fx_pcihost_realize() rely on memory_r= egion_init*() having been called on these pointers already=2E All they seem= to do is adding their sub regions=2E The order in which this happens seems= to be irrelevant, otherwise we'd see changes in the QOM console calls I gu= ess=2E > >>=20 >> > } else { =20 >>=20 >>=20 >> > pci_memory =3D NULL; >> > rom_memory =3D system_memory; >> > - i440fx_host =3D NULL; >> > + pci_bus =3D NULL; >> > hole64_size =3D 0; =20 >>=20 >> is it possible to turn these into initializers, and get rid of=20 >> 'else' branch? Sure, this is possible=2E I'd add another patch before this one=2E Best regards, Bernhard >>=20 >> > } >> > =20 >> > @@ -243,29 +268,6 @@ static void pc_init1(MachineState *machine, >> > PIIX3State *piix3; >> > PCIDevice *pci_dev; >> > =20 >> > - object_property_add_child(OBJECT(machine), "i440fx", i440fx_= host); >> > - object_property_set_link(i440fx_host, PCI_HOST_PROP_RAM_MEM, >> > - OBJECT(ram_memory), &error_fatal); >> > - object_property_set_link(i440fx_host, PCI_HOST_PROP_PCI_MEM, >> > - OBJECT(pci_memory), &error_fatal); >> > - object_property_set_link(i440fx_host, PCI_HOST_PROP_SYSTEM_M= EM, >> > - OBJECT(system_memory), &error_fatal= ); >> > - object_property_set_link(i440fx_host, PCI_HOST_PROP_IO_MEM, >> > - OBJECT(system_io), &error_fatal); >> > - object_property_set_uint(i440fx_host, PCI_HOST_BELOW_4G_MEM_= SIZE, >> > - x86ms->below_4g_mem_size, &error_fa= tal); >> > - object_property_set_uint(i440fx_host, PCI_HOST_ABOVE_4G_MEM_= SIZE, >> > - x86ms->above_4g_mem_size, &error_fa= tal); >> > - object_property_set_str(i440fx_host, I440FX_HOST_PROP_PCI_TY= PE, >> > - pci_type, &error_fatal); >> > - sysbus_realize_and_unref(SYS_BUS_DEVICE(i440fx_host), &error= _fatal); >> > - >> > - pci_bus =3D PCI_BUS(qdev_get_child_bus(DEVICE(i440fx_host), = "pci=2E0")); >> > - pci_bus_map_irqs(pci_bus, >> > - xen_enabled() ? xen_pci_slot_get_pirq >> > - : pc_pci_slot_get_pirq); >> > - pcms->bus =3D pci_bus; >> > - >> > pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, tru= e, >> > TYPE_PIIX3_DEVICE)= ; >> > =20 >> > @@ -290,7 +292,6 @@ static void pc_init1(MachineState *machine, >> > rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJEC= T(pci_dev), >> > "rtc"))= ; >> > } else { >> > - pci_bus =3D NULL; >> > isa_bus =3D isa_bus_new(NULL, system_memory, system_io, >> > &error_abort); >> > =20 >>=20 >