From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:46585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RqmZG-00028z-Gq for qemu-devel@nongnu.org; Fri, 27 Jan 2012 09:14:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RqmZF-0002YM-1W for qemu-devel@nongnu.org; Fri, 27 Jan 2012 09:14:18 -0500 Received: from mail-pw0-f45.google.com ([209.85.160.45]:60050) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RqmZE-0002Xt-RU for qemu-devel@nongnu.org; Fri, 27 Jan 2012 09:14:16 -0500 Received: by pbdd2 with SMTP id d2so2058065pbd.4 for ; Fri, 27 Jan 2012 06:14:15 -0800 (PST) Message-ID: <4F22B133.8080102@codemonkey.ws> Date: Fri, 27 Jan 2012 08:14:11 -0600 From: Anthony Liguori MIME-Version: 1.0 References: <1327604460-31142-1-git-send-email-aliguori@us.ibm.com> <1327604460-31142-2-git-send-email-aliguori@us.ibm.com> <4F226562.6010300@siemens.com> <4F22A18C.4090608@codemonkey.ws> <4F22AECA.50800@suse.de> In-Reply-To: <4F22AECA.50800@suse.de> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 01/15] pc: merge pc_piix.c into pc.c List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-15?Q?Andreas_F=E4rber?= Cc: Peter Maydell , Anthony Liguori , Jan Kiszka , qemu-devel@nongnu.org, Markus Armbruster , =?ISO-8859-15?Q?Herv=E9_Poussineau?= , Avi Kivity , Paolo Bonzini On 01/27/2012 08:03 AM, Andreas Färber wrote: > Am 27.01.2012 14:07, schrieb Anthony Liguori: >> [...] My guess is that a SuperIO >> chip could be an ISADevice and that we could simply make the PIIX3 has-a >> SuperIO. Then the ISAPC would have a trivial ISA chipset that has-a >> SuperIO. > > That sounds pretty much like our construction site for PReP... Yup. It basically boils down to: Root Complex[1] (PCI Host) - Northbridge (Memory Controller) - Southbridge (Super I/O chip) Most platforms will follow this type of composition model with peripheral devices hanging off a bus in the Southbridge or directly from the Root Complex. > Would you say that the SuperIO is-a ISADevice The SuperIO device is-a Root Complex device. With the I440FX, the Root Complex was PCI bus so the SuperIO chip (the PIIX3) is-a PCIDevice. In older PCIs, the Root Complex was ISA (sort of). [1] A better name for this is System Bus but I'm using Root Complex to avoid confusion with sysbus. But for the PC, we can make the SuperIO chip be is-a DeviceState and just have it expose a MemoryRegion and a bunch of IRQs. That would trivialize the implementation of an PIIX3 such that it has-a PCSuperIO and then just routes IRQs appropriately. > and has-a ISADevice or > would you want to remodel all ISADevices associated with a Super I/O > chipset as private devices to mess with their internals without the > whole enable/disable, etc. ugliness we ran into? > > I somewhat doubt that we can find a generic "SuperIO" base class btw. Right, it's unlikely that a PC SuperIO chip would be useful outside of a PC. But you may find certain classes of platforms all have a common SuperI/O chip and can model similar things. Regards, Anthony Liguori > Andreas >