From: Gerd Hoffmann <kraxel@redhat.com>
To: Alexey Korolev <alexey.korolev@endace.com>
Cc: sfd@endace.com, seabios@seabios.org, mst@redhat.com,
qemu-devel@nongnu.org, avi@redhat.com
Subject: Re: [Qemu-devel] [SeaBIOS] [PATCH 4/6] Mapping of BARs and Bridge regions
Date: Fri, 02 Mar 2012 08:21:32 +0100 [thread overview]
Message-ID: <4F5074FC.3080500@redhat.com> (raw)
In-Reply-To: <4F4FF1AC.40601@endace.com>
On 03/01/12 23:01, Alexey Korolev wrote:
> On 01/03/12 22:22, Gerd Hoffmann wrote:
>> On 03/01/12 07:57, Alexey Korolev wrote:
>>> In pci_bios_map_regions() we try to reserve memory for
>>> all entries of root bus regions.
>>> If pci_bios_init_root_regions() fails - e.g no enough space, we create two new pci_regions:
>>> r64pref, r64mem and migrate all entries which are 64bit capable to them. Migration process
>>> is very simple: delete the entry from one list add to another.
>> It isn't that simple. There are a bunch of constrains. First the
>> bridge must be 64bit capable. All bridges up to the root bus in case of
>> nested bridges. Second all other prefmem bars of devices behind the
>> bridge must be 64bit capable too. Again, in case of nested bridges this
>> applies to all devices behind the toplevel bridge.
> It must be simple as we derive 64bit flag from devices behind the bridge at the stage of building topology.
>
> In other words if the entry at the stage of mapping has 64bit flag it means that the entry and all
> the entries behind it are 64bit capable.
>
> + for (i = (MaxPCIBus + 1) * PCI_REGION_TYPE_COUNT ; i < 0; i--) {
> + .................
> + is64bit = this_entry->is64bit;
> + size = 0;
> + foreach_region_entry(®ions[i-1], entry) {
> + size += entry->size;
> + is64bit &= entry->is64bit;
> + }
> .................
> + this_entry->is64bit = is64bit;
This pass looks at the children and clears the is64bit in the parent in
case one of the children isn't 64bit capable.
I think you need a second pass here, clearing the is64bit in all
children in case the parent has is64bit cleared.
cheers,
Gerd
next prev parent reply other threads:[~2012-03-02 7:22 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-01 5:50 [Qemu-devel] [Seabios] [PATCH 0/6] 64bit PCI BARs allocations (take 2) Alexey Korolev
2012-03-01 6:05 ` [Qemu-devel] [Seabios] [PATCH 1/6] Adding new structures Alexey Korolev
2012-03-01 6:15 ` [Qemu-devel] [PATCH 2/6] New service functions and ported old functions to 64bit Alexey Korolev
2012-03-01 6:40 ` [Qemu-devel] [PATCH 3/6] Fill PCI regions with etnries Alexey Korolev
2012-03-01 6:57 ` [Qemu-devel] [PATCH 4/6] Mapping of BARs and Bridge regions Alexey Korolev
2012-03-01 9:22 ` [Qemu-devel] [SeaBIOS] " Gerd Hoffmann
2012-03-01 22:01 ` Alexey Korolev
2012-03-02 7:21 ` Gerd Hoffmann [this message]
2012-03-05 5:31 ` Alexey Korolev
2012-03-01 7:02 ` [Qemu-devel] [PATCH 5/6] Delete old code Alexey Korolev
2012-03-01 7:11 ` [Qemu-devel] [PATCH 6/6] 64bit PCI range in _CRS table Alexey Korolev
2012-03-01 9:05 ` [Qemu-devel] [SeaBIOS] [Seabios] [PATCH 0/6] 64bit PCI BARs allocations (take 2) Gerd Hoffmann
2012-03-01 21:48 ` Alexey Korolev
2012-03-02 7:08 ` Gerd Hoffmann
2012-03-05 5:34 ` Alexey Korolev
2012-03-05 10:12 ` Gerd Hoffmann
2012-03-06 4:28 ` Alexey Korolev
2012-03-04 19:40 ` [Qemu-devel] " Kevin O'Connor
2012-03-05 6:03 ` Alexey Korolev
2012-03-05 13:16 ` Kevin O'Connor
2012-03-05 9:53 ` [Qemu-devel] [SeaBIOS] " Gerd Hoffmann
2012-03-05 13:49 ` Kevin O'Connor
2012-03-06 4:44 ` Alexey Korolev
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