From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56211) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3UvJ-0002np-8i for qemu-devel@nongnu.org; Fri, 02 Mar 2012 11:01:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S3UvH-00006j-EZ for qemu-devel@nongnu.org; Fri, 02 Mar 2012 11:01:36 -0500 Received: from mail-pw0-f45.google.com ([209.85.160.45]:40585) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S3UvH-00006Z-8R for qemu-devel@nongnu.org; Fri, 02 Mar 2012 11:01:35 -0500 Received: by pbcuo5 with SMTP id uo5so1343942pbc.4 for ; Fri, 02 Mar 2012 08:01:32 -0800 (PST) Message-ID: <4F50EED9.4000101@codemonkey.ws> Date: Fri, 02 Mar 2012 10:01:29 -0600 From: Anthony Liguori MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] IRQ number, interrupt number, interrupt line & GPIO[in/out] List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Zhi Yong Wu Cc: QEMU Developers Hi Zhi Yong, On 03/02/2012 06:38 AM, Zhi Yong Wu wrote: > HI, > > Can anyone explain their relationship and difference among them? It > is very appreciated if you can make some comments. thanks. IRQ == interrupt. GPIO is just another name for an input or output pin on a chip which could be a IRQ line. Interrupt controllers can receive interrupts from one or more devices. Usually, the input pins on an interrupt controller can be numbered sequentially. When we say that the first UART is on IRQ number 3, what that really means is that the IRQ output pin on the UART chip is connected to pin number 3 on the interrupt controller with a wire. But there never is a single interrupt controller in a real system. For instance, a PCI bus has it's own interrupt controller that has four input pins (called LNKs) that are oddly labeled A, B, C, D. For the I440FX PCI bus, those four input pins are mapped to two IRQs which are then connected to the I/O APIC. Regards, Anthony Liguori