From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46670) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S4m1A-0001pZ-Rh for qemu-devel@nongnu.org; Mon, 05 Mar 2012 23:28:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S4m19-0006OR-4m for qemu-devel@nongnu.org; Mon, 05 Mar 2012 23:28:56 -0500 Received: from usrksweb02.endace.com ([174.143.168.194]:51536) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S4m18-0006OL-US for qemu-devel@nongnu.org; Mon, 05 Mar 2012 23:28:55 -0500 Message-ID: <4F559272.4050105@endace.com> Date: Tue, 6 Mar 2012 17:28:34 +1300 From: Alexey Korolev MIME-Version: 1.0 References: <1330581043.29508.61.camel@nzhmlwks0057.ad.endace.com> <4F4F3BF2.7040003@redhat.com> <4F4FEECB.3060901@endace.com> <4F5071DA.5020101@redhat.com> <4F545052.1060406@endace.com> <4F549176.6070404@redhat.com> In-Reply-To: <4F549176.6070404@redhat.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [SeaBIOS] [Seabios] [PATCH 0/6] 64bit PCI BARs allocations (take 2) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: sfd@endace.com, avi@redhat.com, seabios@seabios.org, qemu-devel@nongnu.org, mst@redhat.com On 05/03/12 23:12, Gerd Hoffmann wrote: > Hi, > >> I can either send a patch over existing patches, or send new series or both. > For testing a incremental patch is fine, for merge a new series with the > fixes squashed into the buggy patches is needed. > > cheers, > Gerd Sure. Here are the hot fixes for the "bridge" test, please apply the patch over this series: diff --git a/src/pciinit.c b/src/pciinit.c index 9c41e3c..384209d 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -326,10 +326,14 @@ pci_bios_init_bus(void) static u64 pci_size_roundup(u64 size) { - int index = __fls((u32)((size - 1) >> 32)); - if (!index) - index = __fls((u32)(size - 1)); - return 0x1 << (index + 1); + int rest = !!(size & (size - 1)); + int index; + if (size >> 32) { + index = __fls((u32)(size >> 32)); + return 0x1ULL << (index + rest + 32); + } + index = __fls((u32)(size)); + return 0x1ULL << (index + rest); } static u64 @@ -372,6 +376,18 @@ pci_get_bar_size(struct pci_device *pci, int bar, return (u32)((~(sz & mask)) + 1); } +static int pci_bridge_is64bit(struct pci_device *pci) +{ + u32 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE); + if (!pmem) { + pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0); + pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE); + pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0); + } + if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) + return 1; + return 0; +} static u64 pci_region_max_size(struct pci_region *r) { u64 max = 0; @@ -446,7 +462,9 @@ static int pci_bios_fill_regions(struct pci_region *regions) for (type = 0; type < PCI_REGION_TYPE_COUNT; type++, this_region++, parent++) { /* Only prefetchable bridge regions can be 64bit */ - is64bit = (type == PCI_REGION_TYPE_PREFMEM); + is64bit = 0; + if (type == PCI_REGION_TYPE_PREFMEM) + is64bit = pci_bridge_is64bit(pci); entry = pci_region_create_entry(parent, pci, 0, type, is64bit); if (!entry) return -1; @@ -475,7 +493,7 @@ static int pci_bios_fill_regions(struct pci_region *regions) } } - for (i = (MaxPCIBus + 1) * PCI_REGION_TYPE_COUNT ; i < 0; i--) { + for (i = (MaxPCIBus + 1) * PCI_REGION_TYPE_COUNT; i > 0; i--) { struct pci_region_entry *this_entry = regions[i-1].this_entry; if(!this_entry) continue; @@ -491,7 +509,7 @@ static int pci_bios_fill_regions(struct pci_region *regions) size = (size > min_size) ? size : min_size; this_entry->is64bit = is64bit; this_entry->size = pci_size_roundup(size); - dump_entry(entry); + dump_entry(this_entry); } return 0; }