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From: Alexey Starikovskiy <aystarik@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, Paul Brook <paul@codesourcery.com>
Subject: Re: [Qemu-devel] Minimal ARM LPAE support
Date: Tue, 13 Mar 2012 19:27:31 +0400	[thread overview]
Message-ID: <4F5F6763.8070209@gmail.com> (raw)
In-Reply-To: <CAFEAcA_Bv6-17NKKDT3LpW+xj8BNfHo2Oz6Q=mXki-YuDsCx_Q@mail.gmail.com>

On 03/13/2012 07:14 PM, Peter Maydell wrote:
>>> >>  This change seems to drop the MCRR block cache op handling and I don't
>>> >>  see anything elsewhere which implements it. This will presumably break
>>> >>  some CPU/guest combination.
>> >
>> >  Do you have any pointer on that exactly did we try to emulate here?
> No. You'll need to check the TRMs for every CPU core we claim to
> emulate and the ARM ARM (including the ARMv6 and ARMv5 versions
> as well as the current revision). Yes, this is a really painful
> chore. You'll also need to try to round up some images so you can
> test at least a handful of them.
>
> (I've been ploughing through this for the 32 bit registers as part
> of trying to convert them to a more data driven implementation.)
>
There is B3.15.1 block in the ARM ARM, it says that there were no 64-bit access to system registers before LPAE and Generic Timer. Do you mean that some 64-bit system registers were defined for specific CPUs?

Thanks,
Alex.

  reply	other threads:[~2012-03-13 15:28 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-13 11:19 [Qemu-devel] Minimal ARM LPAE support Alexey Starikovskiy
2012-03-13 13:45 ` Mark Langsdorf
2012-03-13 14:21 ` Peter Maydell
2012-03-13 14:51   ` Alexey Starikovskiy
2012-03-13 15:14     ` Peter Maydell
2012-03-13 15:27       ` Alexey Starikovskiy [this message]
2012-03-13 15:50         ` Peter Maydell
2012-03-13 17:21           ` [Qemu-devel] [PATCH 0/3] " Alexey Starikovskiy

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