From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:42444) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SB7kK-00025E-BY for qemu-devel@nongnu.org; Fri, 23 Mar 2012 12:53:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SB7kF-0006ec-0V for qemu-devel@nongnu.org; Fri, 23 Mar 2012 12:53:47 -0400 Received: from cantor2.suse.de ([195.135.220.15]:35932 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SB7kE-0006eJ-Mz for qemu-devel@nongnu.org; Fri, 23 Mar 2012 12:53:42 -0400 Message-ID: <4F6CAA94.2080406@suse.de> Date: Fri, 23 Mar 2012 17:53:40 +0100 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331689198-11076-1-git-send-email-afaerber@suse.de> <1331710379.2389.15.camel@epip-laptop> In-Reply-To: <1331710379.2389.15.camel@epip-laptop> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: gxt@mprc.pku.edu.cn Cc: qemu-devel@nongnu.org, Anthony Liguori Am 14.03.2012 08:32, schrieb Guan Xuetao: > On Wed, 2012-03-14 at 02:39 +0100, Andreas F=C3=A4rber wrote: >> Based on qom-cpu v4 and object_class_get_list() v2, this series conver= ts >> the UniCore32 CPU to QOM. Code-wise, target-unicore32 is pretty close = to >> target-arm and faces a similar issue of CPU-dependent init code, so le= t's >> tackle it next. >> >> Patch 1 adds a UniCore32 CPU guest core (TCG) section to MAINTAINERS, >> so that the target-unicore32 author gets notified of patches against h= is code. >> >> Patch 2, based on feedback from Guan Xuetao, changes the license of mo= st >> target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a >> qemu_malloc() -> g_malloc() substitution that he can't relicense at th= is time, >> so leave that as GPLv2 and declare my following patches explicitly as = GPLv2+. >> >> Patch 2 embeds CPUUniCore32State into UniCore32CPU. My new cpu-qom.h h= eader >> can be GPLv2+, but into cpu.c we're moving helper.c code so make it GP= Lv2 for now. >> >> Patches 4-7 move code out of the uc32_cpu_init() function and into cla= sses. >=20 > I pulled the latest qemu code, but these patches seems to rely on the > former qom-cpu v4 series. That series has been applied in the meantime, so unicore32 should no longer depend on other series. > Could you tell me where I can pull the testable branch/tree? Sorry, repo.or.cz was having problems at the time of posting, this v1 series is now available at: git://repo.or.cz/qemu/afaerber.git qom-cpu-unicore32.v1 http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-cpu-unicore= 32.v1 I've added links to the Wiki for my work-in-progress branches on GitHub: http://wiki.qemu.org/Features/QOM/CPU Today I've reworked the preceding ARM series and rebased onto v5; I still need to revisit the table-driven class initialization before sending out a v2. MAINTAINERS and licenses are already adjusted. Regards, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg