From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:36143) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDZe2-0005Tb-0e for qemu-devel@nongnu.org; Fri, 30 Mar 2012 07:05:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SDZe0-0005Tw-Bg for qemu-devel@nongnu.org; Fri, 30 Mar 2012 07:05:25 -0400 Received: from mail-qa0-f52.google.com ([209.85.216.52]:36397) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SDZe0-0005Tn-5I for qemu-devel@nongnu.org; Fri, 30 Mar 2012 07:05:24 -0400 Received: by qabg40 with SMTP id g40so302563qab.4 for ; Fri, 30 Mar 2012 04:05:22 -0700 (PDT) Sender: Richard Henderson Message-ID: <4F75936F.8030302@twiddle.net> Date: Fri, 30 Mar 2012 07:05:19 -0400 From: Richard Henderson MIME-Version: 1.0 References: <1333077432-22228-1-git-send-email-proljc@gmail.com> <1333077432-22228-9-git-send-email-proljc@gmail.com> In-Reply-To: <1333077432-22228-9-git-send-email-proljc@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH V4 08/11] Add MIPS DSP Bit/Manipulation instructions Support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jia Liu Cc: qemu-devel@nongnu.org, aurelien@aurel32.net On 03/29/2012 11:17 PM, Jia Liu wrote: > + int32_t temp; > + uint32_t rd; > + int i, last; > + > + temp = rt & MIPSDSP_LO; > + rd = 0; > + for (i = 0; i < 16; i++) { > + last = temp % 2; > + temp = temp >> 1; temp should not be signed, as that % doesn't do what you wanted. > + imm3 = tcg_const_i32(imm); > + imm2 = tcg_const_i32(imm); > + imm1 = tcg_const_i32(imm); > + imm0 = tcg_const_i32(imm); > + tcg_gen_shli_i32(imm3, imm3, 24); > + tcg_gen_shli_i32(imm2, imm2, 16); > + tcg_gen_shli_i32(imm1, imm1, 8); > + tcg_gen_or_i32(cpu_gpr[rd], imm3, imm2); > + tcg_gen_or_i32(cpu_gpr[rd], cpu_gpr[rd], imm1); > + tcg_gen_or_i32(cpu_gpr[rd], cpu_gpr[rd], imm0); > + tcg_temp_free(imm3); > + tcg_temp_free(imm2); > + tcg_temp_free(imm1); > + tcg_temp_free(imm0); Err, this is an *immediate*. imm = (ctx->opcode >> 16) & 0xFF; tcg_gen_movi(cpu_gpr[rd], imm * 0x01010101); > + rt3 = tcg_const_i32(0); > + rt2 = tcg_const_i32(0); > + rt1 = tcg_const_i32(0); > + rt0 = tcg_const_i32(0); > + > + tcg_gen_andi_i32(rt3, cpu_gpr[rt], 0xFF); > + tcg_gen_andi_i32(rt2, cpu_gpr[rt], 0xFF); > + tcg_gen_andi_i32(rt1, cpu_gpr[rt], 0xFF); > + tcg_gen_andi_i32(rt0, cpu_gpr[rt], 0xFF); > + > + tcg_gen_shli_i32(rt3, rt3, 24); > + tcg_gen_shli_i32(rt2, rt2, 16); > + tcg_gen_shli_i32(rt1, rt1, 8); > + > + tcg_gen_or_i32(cpu_gpr[rd], rt3, rt2); > + tcg_gen_or_i32(cpu_gpr[rd], cpu_gpr[rd], rt1); > + tcg_gen_or_i32(cpu_gpr[rd], cpu_gpr[rd], rt0); I hadn't been asking for you to inline replv, only repl. But if you want to do this, at least only compute t=rt&0xff once. That said, I suspect the * 0x01010101 trick is fairly efficient on most hosts these days. > + TCGv temp_rt = tcg_const_i32(rt); > + gen_helper_insv(cpu_gpr[rt], cpu_env, > + cpu_gpr[rs], cpu_gpr[rt]); > + tcg_temp_free(temp_rt); temp_rt is unused. r~