From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37390) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SPZAY-0007s5-2S for qemu-devel@nongnu.org; Wed, 02 May 2012 09:00:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SPZAN-0004gv-Qp for qemu-devel@nongnu.org; Wed, 02 May 2012 09:00:33 -0400 Message-ID: <4FA12FE5.8070305@suse.de> Date: Wed, 02 May 2012 15:00:21 +0200 From: Alexander Graf MIME-Version: 1.0 References: <5B21E504-3B25-45B3-8951-5AB66D7833B1@suse.de> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 20/22] ppc: move load and store helpers, switch to AREG0 free mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: malc Cc: Blue Swirl , qemu-ppc@nongnu.org, qemu-devel On 04/30/2012 05:34 PM, malc wrote: > On Mon, 30 Apr 2012, Alexander Graf wrote: > >> On 30.04.2012, at 12:45, Alexander Graf wrote: >> >>> On 22.04.2012, at 15:26, Blue Swirl wrote: >>> >>>> Add an explicit CPUPPCState parameter instead of relying on AREG0 >>>> and rename op_helper.c (which only contains load and store helpers) >>>> to mem_helper.c. Remove AREG0 swapping in >>>> tlb_fill(). >>>> >>>> Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation >>>> and interrupt handling, cpu_{ld,st}{l,uw}_data in loads and stores. >>> This patch breaks qemu-system-ppc64 on ppc32 host user space for me. I'm trying to debug it down, but worst case I'll omit this patch set for 1.1. >> Ok, so apparently nobody ever tested TCG_AREG0 mode with the ppc tcg >> target. It looks as if the >> 64-bit-guest-registers-in-32-bit-host-registers code path is missing >> completely. >> >> This actually makes me less confident that this is a change we want for >> 1.1. I'll remove the patches from the queue. >> >> >> Alex >> >> >> TCG register swizzling code: >> >> #ifdef CONFIG_TCG_PASS_AREG0 >> /* XXX/FIXME: suboptimal */ >> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], >> tcg_target_call_iarg_regs[2]); >> tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[2], >> tcg_target_call_iarg_regs[1]); >> tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], >> tcg_target_call_iarg_regs[0]); >> tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], >> TCG_AREG0); >> #endif >> tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1); >> > The above snippet is incorrect for SysV ppc32 ABI, due to misalignment > of long long argument in register file. Hmm - so what would be the correct version? :) Alex