From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49546) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSFQ3-00080e-Bg for qemu-devel@nongnu.org; Wed, 09 May 2012 18:31:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SSFQ1-0002jG-HM for qemu-devel@nongnu.org; Wed, 09 May 2012 18:31:38 -0400 Received: from cantor2.suse.de ([195.135.220.15]:59054 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSFQ1-0002j8-7j for qemu-devel@nongnu.org; Wed, 09 May 2012 18:31:37 -0400 Message-ID: <4FAAF046.3060004@suse.de> Date: Thu, 10 May 2012 00:31:34 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH for 1.1-rc1] mce_init should be called after parsing cpu_model List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Mammedov Cc: mdroth@linux.vnet.ibm.com, aliguori@us.ibm.com, qemu-devel@nongnu.org, ehabkost@redhat.com Am 09.05.2012 21:49, schrieb Igor Mammedov: > ----- Original Message ----- >> From: "Andreas F=C3=A4rber" >> Am 09.05.2012 21:01, schrieb Igor Mammedov: >>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c >>> index 65d9af6..5d11e7b 100644 >>> --- a/target-i386/cpu.c >>> +++ b/target-i386/cpu.c >>> @@ -1153,6 +1153,22 @@ void x86_cpu_list(FILE *f, fprintf_function >>> cpu_fprintf, const char *optarg) >>> } >>> } >>> =20 >>> +static void mce_init(X86CPU *cpu) >>> +{ >>> + CPUX86State *cenv =3D &cpu->env; >>> + unsigned int bank; >>> + >>> + if (((cenv->cpuid_version >> 8) & 0xf) >=3D 6 >>> + && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) =3D=3D >>> + (CPUID_MCE | CPUID_MCA)) { >>> + cenv->mcg_cap =3D MCE_CAP_DEF | MCE_BANKS_DEF; >>> + cenv->mcg_ctl =3D ~(uint64_t)0; >>> + for (bank =3D 0; bank < MCE_BANKS_DEF; bank++) { >>> + cenv->mce_banks[bank * 4] =3D ~(uint64_t)0; >>> + } >>> + } >>> +} >>> + >>> int cpu_x86_register(X86CPU *cpu, const char *cpu_model) >>> { >>> CPUX86State *env =3D &cpu->env; >>> @@ -1204,6 +1220,8 @@ int cpu_x86_register(X86CPU *cpu, const char >>> *cpu_model) >>> error_free(error); >>> return -1; >>> } >>> + >>> + mce_init(cpu); >> >> This would be okay as a short-term rc1 fix. >=20 > Exactly, it is intended as short term fix for 1.1, just noticed that > mce_init was moved before cpuid_* are initialized. No doubt should that be fixed for 1.1. Hearing that 1.1-rc1 is already well under way and in testing, it seems we can give this some more thought and review. I've posted an alternative patch that we could merge for 1.1-rc2. As previously suggested for target-sh4 (where it didn't matter), it avoids a dependency on Paolo's series, which we will definitely not get during Hard Freeze, while remaining compatible to it for future assignment in class_init. Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg