From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49579) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSPvo-0002iv-8d for qemu-devel@nongnu.org; Thu, 10 May 2012 05:45:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SSPvd-0001si-V3 for qemu-devel@nongnu.org; Thu, 10 May 2012 05:45:07 -0400 Message-ID: <4FAB8E14.8070406@suse.de> Date: Thu, 10 May 2012 11:44:52 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1336608729-30289-1-git-send-email-afaerber@suse.de> In-Reply-To: <1336608729-30289-1-git-send-email-afaerber@suse.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH next v2 00/74] QOM CPUState, part 3: CPU reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Riku Voipio , Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , Paolo Bonzini , qemu-ppc , Anthony Liguori , Igor Mammedov , "Edgar E. Iglesias" , Aurelien Jarno , Richard Henderson Am 10.05.2012 02:10, schrieb Andreas F=C3=A4rber: > Andreas F=C3=A4rber (74): > target-arm: Use cpu_reset() in cpu_arm_init() > target-mips: Use cpu_reset() in cpu_mips_init() > target-i386: Pass X86CPU to do_cpu_{init,sipi}() > target-i386: Let cpu_x86_init() return X86CPU Sorry, apparently I ran into some server maintenance of ours while sending - it stopped here saying that the domain us.ibm.com didn't exist. ;) Please ignore this thread, I resent - sorry for the duplicates. Andreas > pc: Use cpu_x86_init() to obtain X86CPU > pc: Pass X86CPU to pc_cpu_reset() > target-sparc: Let cpu_sparc_init() return SPARCCPU > sun4m: Use cpu_sparc_init() to obtain SPARCCPU > sun4m: Pass SPARCCPU to {main,secondary}_cpu_reset() > sun4u: Use cpu_sparc_init() to obtain SPARCCPU > sun4u: Let cpu_devinit() return SPARCCPU > sun4u: Store SPARCCPU in ResetData > leon3: Use cpu_sparc_init() to obtain SPARCCPU > leon3: Store SPARCCPU in ResetData > target-ppc: Let cpu_ppc_init() return PowerPCCPU > ppce500_mpc8544ds: Pass PowerPCCPU to mpc8544ds_cpu_reset[_sec] > spapr: Use cpu_ppc_init() to obtain PowerPCCPU > spapr: Pass PowerPCCPU to spapr_cpu_reset() > ppc440_bamboo: Use cpu_ppc_init() to obtain PowerPCCPU > ppc440_bamboo: Pass PowerPCCPU to main_cpu_reset() > ppc4xx_devs: Use cpu_ppc_init() to obtain PowerPCCPU > ppc4xx_devs: Pass PowerPCCPU to ppc4xx_reset() > ppc_newworld: Use cpu_ppc_init() to obtain PowerPCCPU > ppc_newworld: Pass PowerPCCPU to ppc_core99_reset() > ppc_oldworld: Use cpu_ppc_init() to obtain PowerPCCPU > ppc_oldworld: Pass PowerPCCPU to ppc_heathrow_reset() > ppc_prep: Use cpu_ppc_init() to obtain PowerPCCPU > ppc_prep: Pass PowerPCCPU to ppc_prep_reset() > virtex_ml507: Use cpu_ppc_init() to obtain PowerPCCPU > virtex_ml507: Let ppc440_init_xilinx() return PowerPCCPU > virtex_ml507: Pass PowerPCCPU to main_cpu_reset() > cpu-exec: Use cpu_reset() in cpu_exec() for TARGET_PPC > pxa2xx: Use cpu_arm_init() and store ARMCPU > omap: Use cpu_arm_init() to store ARMCPU in omap_mpu_state_s > armv7m: Use cpu_arm_init() to obtain ARMCPU > armv7m: Pass ARMCPU to armv7m_reset() > arm_boot: Pass ARMCPU to do_cpu_reset() > target-sh4: Let cpu_sh4_init() return SuperHCPU > r2d: Use cpu_sh4_init() to obtain SuperHCPU > r2d: Store SuperHCPU in ResetData > target-lm32: Let cpu_lm32_init() return LM32CPU > lm32_boards: Use cpu_lm32_init() to obtain LM32CPU > lm32_boards: Store LM32CPU in ResetInfo > milkymist: Use cpu_lm32_init() to obtain LM32CPU > milkymist: Store LM32 in ResetInfo > target-xtensa: Let cpu_xtensa_init() return XtensaCPU > xtensa_sim: Use cpu_xtensa_init() to obtain XtensaCPU > xtensa_sim: Pass XtensaCPU to sim_reset() > xtensa_lx60: Use cpu_xtensa_init() to obtain XtensaCPU > xtensa_lx60: Pass XtensaCPU to lx60_reset() > target-cris: Reindent cpu_cris_init() > target-cris: Let cpu_cris_init() return CRISCPU > axis_dev88: Use cpu_cris_init() to obtain CRISCPU > cris-boot: Pass CRISCPU to cris_load_image() > cris-boot: Pass CRISCPU to main_cpu_reset(). > target-microblaze: Let cpu_mb_init() return MicroBlazeCPU > petalogix_ml605: Use cpu_mb_init() to obtain MicroBlazeCPU > petalogix_s3adsp1800_mmu: Use cpu_mb_init() to obtain MicroBlazeCPU > microblaze_boot: Pass MicroBlazeCPU to microblaze_load_kernel() > target-mips: Use cpu_reset() in do_interrupt() > target-mips: Let cpu_mips_init() return MIPSCPU > mips_fulong2e: Use cpu_mips_cpu() to obtain MIPSCPU > mips_fulong2e: Pass MIPSCPU to main_cpu_reset() > mips_jazz: Use cpu_mips_init() to obtain MIPSCPU > mips_jazz: Pass MIPSCPU to main_cpu_reset() > mips_malta: Use cpu_mips_init() to obtain MIPSCPU > mips_malta: Pass MIPSCPU to main_cpu_reset() > mips_mipssim: Use cpu_mips_init() to obtain MIPSCPU > mips_mipssim: Store MIPSCPU in ResetData > mips_r4k: Use cpu_mips_init() to obtain MIPSCPU > mips_r4k: Store MIPSCPU in ResetData > bsd-user: Use cpu_reset() in after cpu_init() > linux-user: Use cpu_reset() after cpu_init() / cpu_copy() > Kill off cpu_state_reset() --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg