[Qemu-devel] [PATCH 0/4, master+QEMU 1.1] sparc64: let's boot Linux!

[Qemu-devel] [PATCH 0/4, master+QEMU 1.1] sparc64: let's boot Linux!

[Artyom Tarasenko]

This small patch series fixes two bugs (patches 1 and 3), 
one reggression (patch 2) and and adds two missing registers 
to apb_pci (patch 4).

The most visible effect: it makes possible booting Linux/sparc64!
Currently not from an IDE disk, but virtio is working just fine:

http://tyom.blogspot.de/2012/05/booting-linuxsparc64-on-todays-openbios.html

/Happy hacking

Artyom Tarasenko (4):
  Implement address masking for SPARC v9 CPUs
  fix block loads broken in commit 30038fd818
  sun4u: initialize OBIO interrupt mappings
  sun4u: implement interrupt clearing registers

 hw/apb_pci.c               |   18 ++++++++++++++++++
 target-sparc/ldst_helper.c |    4 ++--
 target-sparc/translate.c   |   25 ++++++++++++++++++++++++-
 3 files changed, 44 insertions(+), 3 deletions(-)

[Qemu-devel] [PATCH 1/4] Implement address masking for SPARC v9 CPUs

[Artyom Tarasenko]

According to UltraSPARC - IIi User's manual:

14.1.11 Address Masking (Impdep #125)
When PSTATE.AM=1, the CALL, JMPL, and RDPC instructions and all traps
transmit zero in the high-order 32-bits of the PC to their specified destination
registers.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 target-sparc/translate.c |   25 ++++++++++++++++++++++++-
 1 files changed, 24 insertions(+), 1 deletions(-)

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 4967152..b95f91c 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1343,6 +1343,11 @@ static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
     target_ulong target = dc->pc + offset;
 
+#ifdef TARGET_SPARC64
+    if (unlikely(AM_CHECK(dc))) {
+        target &= 0xffffffffULL;
+    }
+#endif
     if (cond == 0x0) {
         /* unconditional not taken */
         if (a) {
@@ -1388,6 +1393,11 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
     target_ulong target = dc->pc + offset;
 
+#ifdef TARGET_SPARC64
+    if (unlikely(AM_CHECK(dc))) {
+        target &= 0xffffffffULL;
+    }
+#endif
     if (cond == 0x0) {
         /* unconditional not taken */
         if (a) {
@@ -1434,6 +1444,9 @@ static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
     target_ulong target = dc->pc + offset;
 
+    if (unlikely(AM_CHECK(dc))) {
+        target &= 0xffffffffULL;
+    }
     flush_cond(dc, r_cond);
     gen_cond_reg(r_cond, cond, r_reg);
     if (a) {
@@ -2486,6 +2499,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
             tcg_temp_free(r_const);
             target += dc->pc;
             gen_mov_pc_npc(dc, cpu_cond);
+#ifdef TARGET_SPARC64
+            if (unlikely(AM_CHECK(dc))) {
+                target &= 0xffffffffULL;
+            }
+#endif
             dc->npc = target;
         }
         goto jmp_insn;
@@ -2610,7 +2628,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
                     {
                         TCGv r_const;
 
-                        r_const = tcg_const_tl(dc->pc);
+                        if (unlikely(AM_CHECK(dc))) {
+                            r_const = tcg_const_tl(dc->pc & 0xffffffffULL);
+                        } else {
+                           r_const = tcg_const_tl(dc->pc);
+                        }
                         gen_movl_TN_reg(rd, r_const);
                         tcg_temp_free(r_const);
                     }
@@ -4579,6 +4601,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
                         r_const = tcg_const_i32(3);
                         gen_helper_check_align(cpu_env, cpu_dst, r_const);
                         tcg_temp_free_i32(r_const);
+                        gen_address_mask(dc, cpu_dst);
                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
                         dc->npc = DYNAMIC_PC;
                     }
-- 
1.7.1

[Qemu-devel] [PATCH 2/4, master+QEMU 1.1] fix block loads broken in commit 30038fd818

[Artyom Tarasenko]

Fix UltraSPARC/JPS1/UA2007 VIS block load instructions broken in
30038fd81808f7c3bca92be2369e74c8ca7b3d69

Conflicts:

	target-sparc/ldst_helper.c

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 target-sparc/ldst_helper.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 04ffddf..27660dd 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2098,8 +2098,8 @@ void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
             return;
         }
         helper_check_align(env, addr, 0x3f);
-        for (i = 0; i < 8; i++, rd += 2, addr += 4) {
-            env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
+        for (i = 0; i < 8; i++, rd += 2, addr += 8) {
+            env->fpr[rd/2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
         }
         return;
 
-- 
1.7.1

[Qemu-devel] [PATCH 3/4, master+QEMU 1.1] sun4u: initialize OBIO interrupt mappings

[Artyom Tarasenko]

Similarly to PCI interrupt mappings, the OBIO ones have to be initialized.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 hw/apb_pci.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 7e28808..d4e11bc 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -404,6 +404,9 @@ static void pci_pbm_reset(DeviceState *d)
     for (i = 0; i < 8; i++) {
         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
     }
+    for (i = 0; i < 32; i++) {
+        s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
+    }
 
     if (s->nr_resets++ == 0) {
         /* Power on reset */
@@ -426,6 +429,9 @@ static int pci_pbm_init_device(SysBusDevice *dev)
     for (i = 0; i < 8; i++) {
         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
     }
+    for (i = 0; i < 32; i++) {
+        s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
+    }
     s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
 
     /* apb_config */
-- 
1.7.1

[Qemu-devel] [PATCH 4/4, master+QEMU 1.1] sun4u: implement interrupt clearing registers

[Artyom Tarasenko]

Implement registers for clearing OBIO and PCI interrupts

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 hw/apb_pci.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index d4e11bc..c28411a 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -85,6 +85,8 @@ typedef struct APBState {
     unsigned int nr_resets;
 } APBState;
 
+static void pci_apb_set_irq(void *opaque, int irq_num, int level);
+
 static void apb_config_writel (void *opaque, target_phys_addr_t addr,
                                uint64_t val, unsigned size)
 {
@@ -113,6 +115,16 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
             s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK;
         }
         break;
+    case 0x1400 ... 0x143f: /* PCI interrupt clear */
+        if (addr & 4) {
+            pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0);
+        }
+        break;
+    case 0x1800 ... 0x1860: /* OBIO interrupt clear */
+        if (addr & 4) {
+            pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0);
+        }
+        break;
     case 0x2000 ... 0x202f: /* PCI control */
         s->pci_control[(addr & 0x3f) >> 2] = val;
         break;
-- 
1.7.1

Re: [Qemu-devel] [PATCH 1/4] Implement address masking for SPARC v9 CPUs

[Artyom Tarasenko]

Ups, the subject line was supposed to be [PATCH 1/4, master+QEMU 1.1]
... Should I resend?


On Sat, May 12, 2012 at 11:15 AM, Artyom Tarasenko <atar4qemu@gmail.com> wrote:
> According to UltraSPARC - IIi User's manual:
>
> 14.1.11 Address Masking (Impdep #125)
> When PSTATE.AM=1, the CALL, JMPL, and RDPC instructions and all traps
> transmit zero in the high-order 32-bits of the PC to their specified destination
> registers.
>
> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
>  target-sparc/translate.c |   25 ++++++++++++++++++++++++-
>  1 files changed, 24 insertions(+), 1 deletions(-)
>
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index 4967152..b95f91c 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -1343,6 +1343,11 @@ static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
>     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
>     target_ulong target = dc->pc + offset;
>
> +#ifdef TARGET_SPARC64
> +    if (unlikely(AM_CHECK(dc))) {
> +        target &= 0xffffffffULL;
> +    }
> +#endif
>     if (cond == 0x0) {
>         /* unconditional not taken */
>         if (a) {
> @@ -1388,6 +1393,11 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
>     unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
>     target_ulong target = dc->pc + offset;
>
> +#ifdef TARGET_SPARC64
> +    if (unlikely(AM_CHECK(dc))) {
> +        target &= 0xffffffffULL;
> +    }
> +#endif
>     if (cond == 0x0) {
>         /* unconditional not taken */
>         if (a) {
> @@ -1434,6 +1444,9 @@ static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
>     unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
>     target_ulong target = dc->pc + offset;
>
> +    if (unlikely(AM_CHECK(dc))) {
> +        target &= 0xffffffffULL;
> +    }
>     flush_cond(dc, r_cond);
>     gen_cond_reg(r_cond, cond, r_reg);
>     if (a) {
> @@ -2486,6 +2499,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
>             tcg_temp_free(r_const);
>             target += dc->pc;
>             gen_mov_pc_npc(dc, cpu_cond);
> +#ifdef TARGET_SPARC64
> +            if (unlikely(AM_CHECK(dc))) {
> +                target &= 0xffffffffULL;
> +            }
> +#endif
>             dc->npc = target;
>         }
>         goto jmp_insn;
> @@ -2610,7 +2628,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
>                     {
>                         TCGv r_const;
>
> -                        r_const = tcg_const_tl(dc->pc);
> +                        if (unlikely(AM_CHECK(dc))) {
> +                            r_const = tcg_const_tl(dc->pc & 0xffffffffULL);
> +                        } else {
> +                           r_const = tcg_const_tl(dc->pc);
> +                        }
>                         gen_movl_TN_reg(rd, r_const);
>                         tcg_temp_free(r_const);
>                     }
> @@ -4579,6 +4601,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
>                         r_const = tcg_const_i32(3);
>                         gen_helper_check_align(cpu_env, cpu_dst, r_const);
>                         tcg_temp_free_i32(r_const);
> +                        gen_address_mask(dc, cpu_dst);
>                         tcg_gen_mov_tl(cpu_npc, cpu_dst);
>                         dc->npc = DYNAMIC_PC;
>                     }
> --
> 1.7.1
>



-- 
Regards,
Artyom Tarasenko

solaris/sparc under qemu blog: http://tyom.blogspot.com/search/label/qemu

Re: [Qemu-devel] [PATCH 0/4, master+QEMU 1.1] sparc64: let's boot Linux!

[Blue Swirl]

On Sat, May 12, 2012 at 9:15 AM, Artyom Tarasenko <atar4qemu@gmail.com> wrote:
> This small patch series fixes two bugs (patches 1 and 3),
> one reggression (patch 2) and and adds two missing registers
> to apb_pci (patch 4).

Thanks, applied all. I trimmed the patch descriptions (too long lines
or Conflicts: do not look good in git log) and in one patch there was
probably accidental white space change.

>
> The most visible effect: it makes possible booting Linux/sparc64!
> Currently not from an IDE disk, but virtio is working just fine:
>
> http://tyom.blogspot.de/2012/05/booting-linuxsparc64-on-todays-openbios.html

The interrupt mapping hacks call for changes in OpenBIOS, would you
already have patches for that? ;-)

> /Happy hacking
>
> Artyom Tarasenko (4):
>  Implement address masking for SPARC v9 CPUs
>  fix block loads broken in commit 30038fd818
>  sun4u: initialize OBIO interrupt mappings
>  sun4u: implement interrupt clearing registers
>
>  hw/apb_pci.c               |   18 ++++++++++++++++++
>  target-sparc/ldst_helper.c |    4 ++--
>  target-sparc/translate.c   |   25 ++++++++++++++++++++++++-
>  3 files changed, 44 insertions(+), 3 deletions(-)
>

Re: [Qemu-devel] [PATCH 0/4, master+QEMU 1.1] sparc64: let's boot Linux!

[Artyom Tarasenko]

On Sat, May 12, 2012 at 12:01 PM, Blue Swirl <blauwirbel@gmail.com> wrote:
> On Sat, May 12, 2012 at 9:15 AM, Artyom Tarasenko <atar4qemu@gmail.com> wrote:
>> This small patch series fixes two bugs (patches 1 and 3),
>> one reggression (patch 2) and and adds two missing registers
>> to apb_pci (patch 4).
>
> Thanks, applied all. I trimmed the patch descriptions (too long lines
> or Conflicts: do not look good in git log)

Ups. Looks like check_patch.pl doesn't handle this?

> and in one patch there was
> probably accidental white space change.
>
>>
>> The most visible effect: it makes possible booting Linux/sparc64!
>> Currently not from an IDE disk, but virtio is working just fine:
>>
>> http://tyom.blogspot.de/2012/05/booting-linuxsparc64-on-todays-openbios.html
>
> The interrupt mapping hacks call for changes in OpenBIOS, would you
> already have patches for that? ;-)

No. ;-) Can easily cook up a hack patch, but doing it the right way
requires changes
in PCI handling in OpenBIOS. And since the pci code is used across all
the platforms,
I didn't risk to change it.

>
>> /Happy hacking
>>
>> Artyom Tarasenko (4):
>>  Implement address masking for SPARC v9 CPUs
>>  fix block loads broken in commit 30038fd818
>>  sun4u: initialize OBIO interrupt mappings
>>  sun4u: implement interrupt clearing registers
>>
>>  hw/apb_pci.c               |   18 ++++++++++++++++++
>>  target-sparc/ldst_helper.c |    4 ++--
>>  target-sparc/translate.c   |   25 ++++++++++++++++++++++++-
>>  3 files changed, 44 insertions(+), 3 deletions(-)
>>


-- 
Regards,
Artyom Tarasenko

solaris/sparc under qemu blog: http://tyom.blogspot.com/search/label/qemu

Re: [Qemu-devel] [PATCH 4/4, master+QEMU 1.1] sun4u: implement interrupt clearing registers

[Andreas Färber]

Am 12.05.2012 11:15, schrieb Artyom Tarasenko:
> Implement registers for clearing OBIO and PCI interrupts
> 
> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>

Implementing new registers is a feature, not a 1.1 bugfix...
Many of us would like to get patches committed and have to wait.

/-F

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH 4/4, master+QEMU 1.1] sun4u: implement interrupt clearing registers

[Blue Swirl]

On Sat, May 12, 2012 at 11:56 AM, Andreas Färber <afaerber@suse.de> wrote:
> Am 12.05.2012 11:15, schrieb Artyom Tarasenko:
>> Implement registers for clearing OBIO and PCI interrupts
>>
>> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
>
> Implementing new registers is a feature, not a 1.1 bugfix...
> Many of us would like to get patches committed and have to wait.

Those 12 trivial lines in Sparc64 specific code won't destabilize
anything. Two wrongs do not make one right, but several non-bug fix
patches have been committed since start of hard freeze. Including
yours.

>
> /-F
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH 4/4, master+QEMU 1.1] sun4u: implement interrupt clearing registers

[Andreas Färber]

Am 12.05.2012 14:32, schrieb Blue Swirl:
> On Sat, May 12, 2012 at 11:56 AM, Andreas Färber <afaerber@suse.de> wrote:
>> Am 12.05.2012 11:15, schrieb Artyom Tarasenko:
>>> Implement registers for clearing OBIO and PCI interrupts
>>>
>>> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
>>
>> Implementing new registers is a feature, not a 1.1 bugfix...
>> Many of us would like to get patches committed and have to wait.
> 
> Those 12 trivial lines in Sparc64 specific code won't destabilize
> anything. Two wrongs do not make one right, but several non-bug fix
> patches have been committed since start of hard freeze. Including
> yours.

Which do you mean? You have not applied nor reviewed my pending sparc
patches (and I don't expect you to apply them). I've only supplied
bugfix and cleanup patches for 1.1 that I'm aware of.

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH 4/4, master+QEMU 1.1] sun4u: implement interrupt clearing registers

[Artyom Tarasenko]

On Sat, May 12, 2012 at 1:56 PM, Andreas Färber <afaerber@suse.de> wrote:
> Am 12.05.2012 11:15, schrieb Artyom Tarasenko:
>> Implement registers for clearing OBIO and PCI interrupts
>>
>> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
>
> Implementing new registers is a feature, not a 1.1 bugfix...
> Many of us would like to get patches committed and have to wait.

In this case I'd argue, that not having this registers makes the whole
interrupt controller broken, so the patch still can be considered a bug fix.

Also, without this patch the other ones from the series (which are pure fixes)
make no visible effect.

Artyom

>
> /-F
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg


-- 
Regards,
Artyom Tarasenko

solaris/sparc under qemu blog: http://tyom.blogspot.com/search/label/qemu

Re: [Qemu-devel] [PATCH 4/4, master+QEMU 1.1] sun4u: implement interrupt clearing registers

[Blue Swirl]

On Sat, May 12, 2012 at 12:38 PM, Andreas Färber <afaerber@suse.de> wrote:
> Am 12.05.2012 14:32, schrieb Blue Swirl:
>> On Sat, May 12, 2012 at 11:56 AM, Andreas Färber <afaerber@suse.de> wrote:
>>> Am 12.05.2012 11:15, schrieb Artyom Tarasenko:
>>>> Implement registers for clearing OBIO and PCI interrupts
>>>>
>>>> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
>>>
>>> Implementing new registers is a feature, not a 1.1 bugfix...
>>> Many of us would like to get patches committed and have to wait.
>>
>> Those 12 trivial lines in Sparc64 specific code won't destabilize
>> anything. Two wrongs do not make one right, but several non-bug fix
>> patches have been committed since start of hard freeze. Including
>> yours.
>
> Which do you mean? You have not applied nor reviewed my pending sparc
> patches (and I don't expect you to apply them). I've only supplied
> bugfix and cleanup patches for 1.1 that I'm aware of.

For example
f5df5baf11a32ae6a669ac945625d1c3e4deb76d cpu: Update documentation and comment
aabfd88d5e1ec0878aa70076c3de1859614671f4 configure: Reindent VirtFS check

Both are nice, trivial patches, most certainly they don't implement
any registers and the release will be better with those included, but
they are not bug fixes.

>
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH 4/4, master+QEMU 1.1] sun4u: implement interrupt clearing registers

[Andreas Färber]

Am 12.05.2012 15:08, schrieb Blue Swirl:
> On Sat, May 12, 2012 at 12:38 PM, Andreas Färber <afaerber@suse.de> wrote:
>> Am 12.05.2012 14:32, schrieb Blue Swirl:
>>> On Sat, May 12, 2012 at 11:56 AM, Andreas Färber <afaerber@suse.de> wrote:
>>>> Am 12.05.2012 11:15, schrieb Artyom Tarasenko:
>>>>> Implement registers for clearing OBIO and PCI interrupts
>>>>>
>>>>> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
>>>>
>>>> Implementing new registers is a feature, not a 1.1 bugfix...
>>>> Many of us would like to get patches committed and have to wait.
>>>
>>> Those 12 trivial lines in Sparc64 specific code won't destabilize
>>> anything. Two wrongs do not make one right, but several non-bug fix
>>> patches have been committed since start of hard freeze. Including
>>> yours.
>>
>> Which do you mean? You have not applied nor reviewed my pending sparc
>> patches (and I don't expect you to apply them). I've only supplied
>> bugfix and cleanup patches for 1.1 that I'm aware of.
> 
> For example
> f5df5baf11a32ae6a669ac945625d1c3e4deb76d cpu: Update documentation and comment

That one was truely a bug fix. :)

> aabfd88d5e1ec0878aa70076c3de1859614671f4 configure: Reindent VirtFS check

This was a prerequisite for a bug fix that required adding code with
proper indentation.

> Both are nice, trivial patches, most certainly they don't implement
> any registers and the release will be better with those included, but
> they are not bug fixes.

Right, they are cleanups, see above. They do not add random new code.
They might remove dead code. But if the new criteria is "trivial lines
that don't destabilize anything" then I have a 74-patch series for you
to commit on the list (which I'd rather not, respecting the Freeze).

Artyom apparently didn't understand that 1.1 equals master, judging from
$subject, so he is likely unaware of our release process.

Just saying, the same standards should apply to everyone, and that would
include qemu-ga as well.

I do welcome Artyom's sparc64 progress btw. :-)

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

Re: [Qemu-devel] [PATCH 4/4, master+QEMU 1.1] sun4u: implement interrupt clearing registers

[Artyom Tarasenko]

On Sat, May 12, 2012 at 3:57 PM, Andreas Färber <afaerber@suse.de> wrote:
> Am 12.05.2012 15:08, schrieb Blue Swirl:
>> On Sat, May 12, 2012 at 12:38 PM, Andreas Färber <afaerber@suse.de> wrote:
>>> Am 12.05.2012 14:32, schrieb Blue Swirl:
>>>> On Sat, May 12, 2012 at 11:56 AM, Andreas Färber <afaerber@suse.de> wrote:
>>>>> Am 12.05.2012 11:15, schrieb Artyom Tarasenko:
>>>>>> Implement registers for clearing OBIO and PCI interrupts
>>>>>>
>>>>>> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
>>>>>
>>>>> Implementing new registers is a feature, not a 1.1 bugfix...
>>>>> Many of us would like to get patches committed and have to wait.
>>>>
>>>> Those 12 trivial lines in Sparc64 specific code won't destabilize
>>>> anything. Two wrongs do not make one right, but several non-bug fix
>>>> patches have been committed since start of hard freeze. Including
>>>> yours.
>>>
>>> Which do you mean? You have not applied nor reviewed my pending sparc
>>> patches (and I don't expect you to apply them). I've only supplied
>>> bugfix and cleanup patches for 1.1 that I'm aware of.
>>
>> For example
>> f5df5baf11a32ae6a669ac945625d1c3e4deb76d cpu: Update documentation and comment
>
> That one was truely a bug fix. :)
>
>> aabfd88d5e1ec0878aa70076c3de1859614671f4 configure: Reindent VirtFS check
>
> This was a prerequisite for a bug fix that required adding code with
> proper indentation.
>
>> Both are nice, trivial patches, most certainly they don't implement
>> any registers and the release will be better with those included, but
>> they are not bug fixes.
>
> Right, they are cleanups, see above. They do not add random new code.
> They might remove dead code. But if the new criteria is "trivial lines
> that don't destabilize anything" then I have a 74-patch series for you
> to commit on the list (which I'd rather not, respecting the Freeze).
>
> Artyom apparently didn't understand that 1.1 equals master, judging from
> $subject, so he is likely unaware of our release process.

That's true. I thought there is already a branch for 1.1. But, as you
see from the subject, I'd still insist on taking them into 1.1.

> Just saying, the same standards should apply to everyone, and that would
> include qemu-ga as well.

I think our standards are not the part of a cargo cult. ;-) They are
there to improve the quality of the final product. In this particular
case taking the patch does improve the final quality. As you mentioned
in another thread, qemu-system-sparc64 was not very usable until now.
In qemu-1.1 it will be.

> I do welcome Artyom's sparc64 progress btw. :-)

Thanks :-)

>
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg



-- 
Regards,
Artyom Tarasenko

solaris/sparc under qemu blog: http://tyom.blogspot.com/search/label/qemu