From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35913) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1STdhz-0003uD-Rg for qemu-devel@nongnu.org; Sun, 13 May 2012 14:39:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1STdhw-0001Gz-UF for qemu-devel@nongnu.org; Sun, 13 May 2012 14:39:55 -0400 Received: from cantor2.suse.de ([195.135.220.15]:39233 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1STdhw-0001Gf-Lj for qemu-devel@nongnu.org; Sun, 13 May 2012 14:39:52 -0400 Message-ID: <4FAFFFF1.9000403@suse.de> Date: Sun, 13 May 2012 20:39:45 +0200 From: =?ISO-8859-1?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <87vcq7ngxo.fsf@firetop.home> In-Reply-To: <87vcq7ngxo.fsf@firetop.home> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] mips: Fix BC1ANY[24]F instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori , Blue Swirl Cc: rdsandiford@googlemail.com, qemu-devel@nongnu.org Am 26.11.2011 14:37, schrieb Richard Sandiford: > There's some dodgy application of De Morgan's law in the emulation > of the MIPS BC1ANY[24]F instructions: they end up branching only > if all CCs are false, rather than if one CC is. >=20 > Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests. >=20 > Signed-off-by: Richard Sandiford > --- > target-mips/translate.c | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) Ping! Patch has a Reviewed-by. Anthony or Blue, can you apply for 1.1? http://patchwork.ozlabs.org/patch/127798/ /-F > diff --git a/target-mips/translate.c b/target-mips/translate.c > index ba45eb0..2b977b3 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -6017,7 +6017,7 @@ static void gen_compute_branch1 (CPUState *env, D= isasContext *ctx, uint32_t op, > TCGv_i32 t1 =3D tcg_temp_new_i32(); > tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); > tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); > - tcg_gen_nor_i32(t0, t0, t1); > + tcg_gen_nand_i32(t0, t0, t1); > tcg_temp_free_i32(t1); > tcg_gen_andi_i32(t0, t0, 1); > tcg_gen_extu_i32_tl(bcond, t0); > @@ -6041,11 +6041,11 @@ static void gen_compute_branch1 (CPUState *env,= DisasContext *ctx, uint32_t op, > TCGv_i32 t1 =3D tcg_temp_new_i32(); > tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); > tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); > - tcg_gen_or_i32(t0, t0, t1); > + tcg_gen_and_i32(t0, t0, t1); > tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); > - tcg_gen_or_i32(t0, t0, t1); > + tcg_gen_and_i32(t0, t0, t1); > tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); > - tcg_gen_nor_i32(t0, t0, t1); > + tcg_gen_nand_i32(t0, t0, t1); > tcg_temp_free_i32(t1); > tcg_gen_andi_i32(t0, t0, 1); > tcg_gen_extu_i32_tl(bcond, t0); --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg