Re: [Qemu-devel] [PATCH 08/13] iommu: Introduce IOMMU emulation infrastructure

[Anthony Liguori <anthony@codemonkey.ws>]

On 05/15/2012 04:55 PM, Benjamin Herrenschmidt wrote:
> On Tue, 2012-05-15 at 09:02 -0500, Anthony Liguori wrote:
>
>> I think the crux of your argument is that upon a change to the translation
>> table, the operation acts as a barrier such that the exact moment it returns,
>> you're guaranteed that no DMAs are in flight with the old translation mapping.
>
> Not when the translation is changed in memory but whenever the
> translation cache are invalidated or whatever other mechanism the HW
> provides to do that synchronization. On PAPR, this guarantee is provided
> by the H_PUT_TCE hypervisor call which we use to manipulate
> translations.

So this is from the VT-d spec:

"6.2.1 Register Based Invalidation Interface
The register based invalidations provides a synchronous hardware interface for 
invalidations.  Software is expected to write to the IOTLB registers to submit 
invalidation command and may poll on these registers to check for invalidation 
completion. For optimal performance, hardware implementations are recommended to 
complete an invalidation request with minimal latency"

This makes perfect sense.  You write to an MMIO location to request invalidation 
and then *poll* on a separate register for completion.

It's not a single MMIO operation that has an indefinitely return duration.

Regards,

Anthony Liguori