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Subject: Re: [Qemu-devel] [PATCH 01/15] Openrisc: add target stub
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To: Jia Liu <proljc@gmail.com>
Cc: Blue Swirl <blauwirbel@gmail.com>, qemu-devel@nongnu.org

Am 19.05.2012 10:51, schrieb Blue Swirl:
> On Thu, May 17, 2012 at 8:35 AM, Jia Liu <proljc@gmail.com> wrote:
>> +
>> +typedef struct CPUOPENRISCState CPUOPENRISCState;
>> +struct CPUOPENRISCState {
>> +    target_ulong gpr[32];   /* General registers */
>> +    uint32_t sr;            /* Supervisor register */
>> +    target_ulong machi;     /* Multiply register  MACHI */
>> +    target_ulong maclo;     /* Multiply register  MACLO */
>> +    target_ulong fpmaddhi;  /* Multiply and add float register FPMADD=
HI */
>> +    target_ulong fpmaddlo;  /* Multiply and add float register FPMADD=
LO */
>> +    target_ulong epcr;      /* Exception PC register */
>> +    target_ulong eear;      /* Exception EA register */
>> +    uint32_t esr;           /* Exception supervisor register */
>> +    void *irq[32];          /* Interrupt irq input */
>=20
> CPU reset usually zeros all fields up to breakpoints field in
> CPU_COMMON. Then these and the MMU function pointers below would be
> broken, please move below CPU_COMMON.

...or into OpenRISCCPU, if it is not used with offsetof().

/-F

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