* [Qemu-devel] [PATCH 1/9] unicore32-softmmu: make exceptions generated in unicore32 architecture
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
@ 2012-05-25 11:28 ` Guan Xuetao
2012-05-25 11:29 ` [Qemu-devel] [PATCH 2/9] unicore32-softmmu: implement some softmmu specific functions Guan Xuetao
` (9 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:28 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
We need to specify the exception type in proper situations.
Then it could make exceptions generated correctly and timely.
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
cpu-exec.c | 1 +
linux-user/main.c | 3 ++-
target-unicore32/cpu.h | 6 ++++--
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 0344cd5..929b535 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -416,6 +416,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_UNICORE32)
if (interrupt_request & CPU_INTERRUPT_HARD
&& !(env->uncached_asr & ASR_I)) {
+ env->exception_index = UC32_EXCP_INTR;
do_interrupt(env);
next_tb = 0;
}
diff --git a/linux-user/main.c b/linux-user/main.c
index 191b750..a394409 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -958,7 +958,8 @@ void cpu_loop(CPUUniCore32State *env)
}
}
break;
- case UC32_EXCP_TRAP:
+ case UC32_EXCP_DTRAP:
+ case UC32_EXCP_ITRAP:
info.si_signo = SIGSEGV;
info.si_errno = 0;
/* XXX: check env->error_code */
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 81c14ff..66c42f5 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -89,8 +89,10 @@ typedef struct CPUUniCore32State {
#define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
#define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
-#define UC32_EXCP_PRIV (ASR_MODE_PRIV)
-#define UC32_EXCP_TRAP (ASR_MODE_TRAP)
+#define UC32_EXCP_PRIV (1)
+#define UC32_EXCP_ITRAP (2)
+#define UC32_EXCP_DTRAP (3)
+#define UC32_EXCP_INTR (4)
/* Return the current ASR value. */
target_ulong cpu_asr_read(CPUUniCore32State *env1);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH 2/9] unicore32-softmmu: implement some softmmu specific functions
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
2012-05-25 11:28 ` [Qemu-devel] [PATCH 1/9] unicore32-softmmu: make exceptions generated in unicore32 architecture Guan Xuetao
@ 2012-05-25 11:29 ` Guan Xuetao
2012-05-25 11:29 ` [Qemu-devel] [PATCH 3/9] unicore32-softmmu: add coprocessor 0 and ocd instruction support Guan Xuetao
` (8 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:29 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
This patch seperates softmmu functions from the old user-only ones.
So the full exception handlers and page table walking could work now.
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
target-unicore32/helper.c | 25 ++--
target-unicore32/uc32_softmmu.c | 267 +++++++++++++++++++++++++++++++++++++++
2 files changed, 280 insertions(+), 12 deletions(-)
create mode 100644 target-unicore32/uc32_softmmu.c
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 9fe4a37..29e5c78 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -45,19 +45,27 @@ uint32_t HELPER(clz)(uint32_t x)
return clz32(x);
}
+#ifdef CONFIG_USER_ONLY
void do_interrupt(CPUUniCore32State *env)
{
- env->exception_index = -1;
+ cpu_abort(env, "NO interrupt in user mode\n");
}
-int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
- int mmu_idx)
+int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
+ int rw, int mmu_idx)
{
- env->exception_index = UC32_EXCP_TRAP;
- env->cp0.c4_faultaddr = address;
+ cpu_abort(env, "NO mmu fault in user mode\n");
return 1;
}
+void switch_mode(CPUUniCore32State *env, int mode)
+{
+ if (mode != ASR_MODE_USER) {
+ cpu_abort(env, "Tried to switch out of user mode\n");
+ }
+}
+#endif
+
/* These should probably raise undefined insn exceptions. */
void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
{
@@ -84,13 +92,6 @@ uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
return 0;
}
-void switch_mode(CPUUniCore32State *env, int mode)
-{
- if (mode != ASR_MODE_USER) {
- cpu_abort(env, "Tried to switch out of user mode\n");
- }
-}
-
void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
{
cpu_abort(env, "banked r29 write\n");
diff --git a/target-unicore32/uc32_softmmu.c b/target-unicore32/uc32_softmmu.c
new file mode 100644
index 0000000..d5d617b
--- /dev/null
+++ b/target-unicore32/uc32_softmmu.c
@@ -0,0 +1,267 @@
+/*
+ * Softmmu related functions
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#ifdef CONFIG_USER_ONLY
+#error This file only exist under softmmu circumstance
+#endif
+
+#include <cpu.h>
+
+#undef DEBUG_UC32
+
+#ifdef DEBUG_UC32
+#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+#define SUPERPAGE_SIZE (1 << 22)
+#define UC32_PAGETABLE_READ (1 << 8)
+#define UC32_PAGETABLE_WRITE (1 << 7)
+#define UC32_PAGETABLE_EXEC (1 << 6)
+#define UC32_PAGETABLE_EXIST (1 << 2)
+#define PAGETABLE_TYPE(x) ((x) & 3)
+
+
+/* Map CPU modes onto saved register banks. */
+static inline int bank_number(int mode)
+{
+ switch (mode) {
+ case ASR_MODE_USER:
+ case ASR_MODE_SUSR:
+ return 0;
+ case ASR_MODE_PRIV:
+ return 1;
+ case ASR_MODE_TRAP:
+ return 2;
+ case ASR_MODE_EXTN:
+ return 3;
+ case ASR_MODE_INTR:
+ return 4;
+ }
+ cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
+ return -1;
+}
+
+void switch_mode(CPUUniCore32State *env, int mode)
+{
+ int old_mode;
+ int i;
+
+ old_mode = env->uncached_asr & ASR_M;
+ if (mode == old_mode) {
+ return;
+ }
+
+ i = bank_number(old_mode);
+ env->banked_r29[i] = env->regs[29];
+ env->banked_r30[i] = env->regs[30];
+ env->banked_bsr[i] = env->bsr;
+
+ i = bank_number(mode);
+ env->regs[29] = env->banked_r29[i];
+ env->regs[30] = env->banked_r30[i];
+ env->bsr = env->banked_bsr[i];
+}
+
+/* Handle a CPU exception. */
+void do_interrupt(CPUUniCore32State *env)
+{
+ uint32_t addr;
+ int new_mode;
+
+ switch (env->exception_index) {
+ case UC32_EXCP_PRIV:
+ new_mode = ASR_MODE_PRIV;
+ addr = 0x08;
+ break;
+ case UC32_EXCP_ITRAP:
+ DPRINTF("itrap happened at %x\n", env->regs[31]);
+ new_mode = ASR_MODE_TRAP;
+ addr = 0x0c;
+ break;
+ case UC32_EXCP_DTRAP:
+ DPRINTF("dtrap happened at %x\n", env->regs[31]);
+ new_mode = ASR_MODE_TRAP;
+ addr = 0x10;
+ break;
+ case UC32_EXCP_INTR:
+ new_mode = ASR_MODE_INTR;
+ addr = 0x18;
+ break;
+ default:
+ cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+ return;
+ }
+ /* High vectors. */
+ if (env->cp0.c1_sys & (1 << 13)) {
+ addr += 0xffff0000;
+ }
+
+ switch_mode(env, new_mode);
+ env->bsr = cpu_asr_read(env);
+ env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
+ env->uncached_asr |= ASR_I;
+ /* The PC already points to the proper instruction. */
+ env->regs[30] = env->regs[31];
+ env->regs[31] = addr;
+ env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+}
+
+static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
+ int access_type, int is_user, uint32_t *phys_ptr, int *prot,
+ target_ulong *page_size)
+{
+ int code;
+ uint32_t table;
+ uint32_t desc;
+ uint32_t phys_addr;
+
+ /* Pagetable walk. */
+ /* Lookup l1 descriptor. */
+ table = env->cp0.c2_base & 0xfffff000;
+ table |= (address >> 20) & 0xffc;
+ desc = ldl_phys(table);
+ code = 0;
+ switch (PAGETABLE_TYPE(desc)) {
+ case 3:
+ /* Superpage */
+ if (!(desc & UC32_PAGETABLE_EXIST)) {
+ code = 0x0b; /* superpage miss */
+ goto do_fault;
+ }
+ phys_addr = (desc & 0xffc00000) | (address & 0x003fffff);
+ *page_size = SUPERPAGE_SIZE;
+ break;
+ case 0:
+ /* Lookup l2 entry. */
+ if (is_user) {
+ DPRINTF("PGD address %x, desc %x\n", table, desc);
+ }
+ if (!(desc & UC32_PAGETABLE_EXIST)) {
+ code = 0x05; /* second pagetable miss */
+ goto do_fault;
+ }
+ table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
+ desc = ldl_phys(table);
+ /* 4k page. */
+ if (is_user) {
+ DPRINTF("PTE address %x, desc %x\n", table, desc);
+ }
+ if (!(desc & UC32_PAGETABLE_EXIST)) {
+ code = 0x08; /* page miss */
+ goto do_fault;
+ }
+ switch (PAGETABLE_TYPE(desc)) {
+ case 0:
+ phys_addr = (desc & 0xfffff000) | (address & 0xfff);
+ *page_size = TARGET_PAGE_SIZE;
+ break;
+ default:
+ cpu_abort(env, "wrong page type!");
+ }
+ break;
+ default:
+ cpu_abort(env, "wrong page type!");
+ }
+
+ *phys_ptr = phys_addr;
+ *prot = 0;
+ /* Check access permissions. */
+ if (desc & UC32_PAGETABLE_READ) {
+ *prot |= PAGE_READ;
+ } else {
+ if (is_user && (access_type == 0)) {
+ code = 0x11; /* access unreadable area */
+ goto do_fault;
+ }
+ }
+
+ if (desc & UC32_PAGETABLE_WRITE) {
+ *prot |= PAGE_WRITE;
+ } else {
+ if (is_user && (access_type == 1)) {
+ code = 0x12; /* access unwritable area */
+ goto do_fault;
+ }
+ }
+
+ if (desc & UC32_PAGETABLE_EXEC) {
+ *prot |= PAGE_EXEC;
+ } else {
+ if (is_user && (access_type == 2)) {
+ code = 0x13; /* access unexecutable area */
+ goto do_fault;
+ }
+ }
+
+do_fault:
+ return code;
+}
+
+int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
+ int access_type, int mmu_idx)
+{
+ uint32_t phys_addr;
+ target_ulong page_size;
+ int prot;
+ int ret, is_user;
+
+ ret = 1;
+ is_user = mmu_idx == MMU_USER_IDX;
+
+ if ((env->cp0.c1_sys & 1) == 0) {
+ /* MMU disabled. */
+ phys_addr = address;
+ prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ page_size = TARGET_PAGE_SIZE;
+ ret = 0;
+ } else {
+ if ((address & (1 << 31)) || (is_user)) {
+ ret = get_phys_addr_ucv2(env, address, access_type, is_user,
+ &phys_addr, &prot, &page_size);
+ if (is_user) {
+ DPRINTF("user space access: ret %x, address %x, "
+ "access_type %x, phys_addr %x, prot %x\n",
+ ret, address, access_type, phys_addr, prot);
+ }
+ } else {
+ /*IO memory */
+ phys_addr = address | (1 << 31);
+ prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ page_size = TARGET_PAGE_SIZE;
+ ret = 0;
+ }
+ }
+
+ if (ret == 0) {
+ /* Map a single page. */
+ phys_addr &= TARGET_PAGE_MASK;
+ address &= TARGET_PAGE_MASK;
+ tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size);
+ return 0;
+ }
+
+ env->cp0.c3_faultstatus = ret;
+ env->cp0.c4_faultaddr = address;
+ if (access_type == 2) {
+ env->exception_index = UC32_EXCP_ITRAP;
+ } else {
+ env->exception_index = UC32_EXCP_DTRAP;
+ }
+ return ret;
+}
+
+target_phys_addr_t cpu_get_phys_page_debug(CPUUniCore32State *env,
+ target_ulong addr)
+{
+ /* TODO */
+ return addr;
+}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH 3/9] unicore32-softmmu: add coprocessor 0 and ocd instruction support
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
2012-05-25 11:28 ` [Qemu-devel] [PATCH 1/9] unicore32-softmmu: make exceptions generated in unicore32 architecture Guan Xuetao
2012-05-25 11:29 ` [Qemu-devel] [PATCH 2/9] unicore32-softmmu: implement some softmmu specific functions Guan Xuetao
@ 2012-05-25 11:29 ` Guan Xuetao
2012-05-25 11:29 ` [Qemu-devel] [PATCH 4/9] unicore32-softmmu: make sure that kernel can access user space Guan Xuetao
` (7 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:29 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
Coprocessor 0 is system control coprocessor, and we need get/set its contents.
Also, all cache/tlb ops shoule be implemented here, but just ignored with no harm.
OCD (on-chip-debugger) is used for faked console, so we could output chars to
this console without graphic card.
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
target-unicore32/helper.c | 37 --------
target-unicore32/helper.h | 15 ++--
target-unicore32/op_helper.c | 187 +++++++++++++++++++++++++++++++++++++++++-
target-unicore32/translate.c | 73 ++++++++++++++++
4 files changed, 265 insertions(+), 47 deletions(-)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 29e5c78..a06ebf3 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -66,43 +66,6 @@ void switch_mode(CPUUniCore32State *env, int mode)
}
#endif
-/* These should probably raise undefined insn exceptions. */
-void HELPER(set_cp)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
-{
- int op1 = (insn >> 8) & 0xf;
- cpu_abort(env, "cp%i insn %08x\n", op1, insn);
- return;
-}
-
-uint32_t HELPER(get_cp)(CPUUniCore32State *env, uint32_t insn)
-{
- int op1 = (insn >> 8) & 0xf;
- cpu_abort(env, "cp%i insn %08x\n", op1, insn);
- return 0;
-}
-
-void HELPER(set_cp0)(CPUUniCore32State *env, uint32_t insn, uint32_t val)
-{
- cpu_abort(env, "cp0 insn %08x\n", insn);
-}
-
-uint32_t HELPER(get_cp0)(CPUUniCore32State *env, uint32_t insn)
-{
- cpu_abort(env, "cp0 insn %08x\n", insn);
- return 0;
-}
-
-void HELPER(set_r29_banked)(CPUUniCore32State *env, uint32_t mode, uint32_t val)
-{
- cpu_abort(env, "banked r29 write\n");
-}
-
-uint32_t HELPER(get_r29_banked)(CPUUniCore32State *env, uint32_t mode)
-{
- cpu_abort(env, "banked r29 read\n");
- return 0;
-}
-
/* UniCore-F64 support. We follow the convention used for F64 instrunctions:
Single precition routines have a "s" suffix, double precision a
"d" suffix. */
diff --git a/target-unicore32/helper.h b/target-unicore32/helper.h
index 5a3b8a4..11c3726 100644
--- a/target-unicore32/helper.h
+++ b/target-unicore32/helper.h
@@ -8,6 +8,12 @@
*/
#include "def-helper.h"
+#ifndef CONFIG_USER_ONLY
+DEF_HELPER_3(cp0_set, void, i32, i32, i32)
+DEF_HELPER_2(cp0_get, i32, i32, i32)
+DEF_HELPER_1(cp1_putc, void, i32)
+#endif
+
DEF_HELPER_1(clz, i32, i32)
DEF_HELPER_1(clo, i32, i32)
@@ -16,12 +22,6 @@ DEF_HELPER_1(exception, void, i32)
DEF_HELPER_2(asr_write, void, i32, i32)
DEF_HELPER_0(asr_read, i32)
-DEF_HELPER_3(set_cp0, void, env, i32, i32)
-DEF_HELPER_2(get_cp0, i32, env, i32)
-
-DEF_HELPER_3(set_cp, void, env, i32, i32)
-DEF_HELPER_2(get_cp, i32, env, i32)
-
DEF_HELPER_1(get_user_reg, i32, i32)
DEF_HELPER_2(set_user_reg, void, i32, i32)
@@ -38,9 +38,6 @@ DEF_HELPER_2(shr_cc, i32, i32, i32)
DEF_HELPER_2(sar_cc, i32, i32, i32)
DEF_HELPER_2(ror_cc, i32, i32, i32)
-DEF_HELPER_2(get_r29_banked, i32, env, i32)
-DEF_HELPER_3(set_r29_banked, void, env, i32, i32)
-
DEF_HELPER_1(ucf64_get_fpscr, i32, env)
DEF_HELPER_2(ucf64_set_fpscr, void, env, i32)
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index b954c30..aafe86e 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -1,7 +1,7 @@
/*
* UniCore32 helper routines
*
- * Copyright (C) 2010-2011 GUAN Xue-tao
+ * Copyright (C) 2010-2012 Guan Xuetao
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -15,6 +15,14 @@
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
+#undef DEBUG_UC32
+
+#ifdef DEBUG_UC32
+#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
void HELPER(exception)(uint32_t excp)
{
env->exception_index = excp;
@@ -248,3 +256,180 @@ uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
return ((uint32_t)x >> shift) | (x << (32 - shift));
}
}
+
+#ifndef CONFIG_USER_ONLY
+void HELPER(cp0_set)(uint32_t val, uint32_t creg, uint32_t cop)
+{
+ /*
+ * movc pp.nn, rn, #imm9
+ * rn: UCOP_REG_D
+ * nn: UCOP_REG_N
+ * 1: sys control reg.
+ * 2: page table base reg.
+ * 3: data fault status reg.
+ * 4: insn fault status reg.
+ * 5: cache op. reg.
+ * 6: tlb op. reg.
+ * imm9: split UCOP_IMM10 with bit5 is 0
+ */
+ switch (creg) {
+ case 1:
+ if (cop != 0) goto unrecognized;
+ env->cp0.c1_sys = val;
+ break;
+ case 2:
+ if (cop != 0) goto unrecognized;
+ env->cp0.c2_base = val;
+ break;
+ case 3:
+ if (cop != 0) goto unrecognized;
+ env->cp0.c3_faultstatus = val;
+ break;
+ case 4:
+ if (cop != 0) goto unrecognized;
+ env->cp0.c4_faultaddr = val;
+ break;
+ case 5:
+ switch(cop) {
+ case 28:
+ DPRINTF("Invalidate Entire I&D cache\n");
+ return;
+ case 20:
+ DPRINTF("Invalidate Entire Icache\n");
+ return;
+ case 12:
+ DPRINTF("Invalidate Entire Dcache\n");
+ return;
+ case 10:
+ DPRINTF("Clean Entire Dcache\n");
+ return;
+ case 14:
+ DPRINTF("Flush Entire Dcache\n");
+ return;
+ case 13:
+ DPRINTF("Invalidate Dcache line\n");
+ return;
+ case 11:
+ DPRINTF("Clean Dcache line\n");
+ return;
+ case 15:
+ DPRINTF("Flush Dcache line\n");
+ return;
+ }
+ break;
+ case 6:
+ if ((cop <= 6) && (cop >=2)) {
+ /* invalid all tlb */
+ tlb_flush(env, 1);
+ return;
+ }
+ break;
+ default:
+ goto unrecognized;
+ }
+ return;
+unrecognized:
+ cpu_abort(env, "Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+ creg, cop);
+}
+
+uint32_t HELPER(cp0_get)(uint32_t creg, uint32_t cop)
+{
+ /*
+ * movc rd, pp.nn, #imm9
+ * rd: UCOP_REG_D
+ * nn: UCOP_REG_N
+ * 0: cpuid and cachetype
+ * 1: sys control reg.
+ * 2: page table base reg.
+ * 3: data fault status reg.
+ * 4: insn fault status reg.
+ * imm9: split UCOP_IMM10 with bit5 is 0
+ */
+ switch (creg) {
+ case 0:
+ switch (cop) {
+ case 0:
+ return env->cp0.c0_cpuid;
+ case 1:
+ return env->cp0.c0_cachetype;
+ }
+ break;
+ case 1:
+ if (cop == 0) {
+ return env->cp0.c1_sys;
+ }
+ break;
+ case 2:
+ if (cop == 0) {
+ return env->cp0.c2_base;
+ }
+ break;
+ case 3:
+ if (cop == 0) {
+ return env->cp0.c3_faultstatus;
+ }
+ break;
+ case 4:
+ if (cop == 0) {
+ return env->cp0.c4_faultaddr;
+ }
+ break;
+ }
+ cpu_abort(env, "Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
+ creg, cop);
+}
+
+void HELPER(cp1_putc)(target_ulong x)
+{
+ printf("%c", x);
+ fflush(NULL);
+ return;
+}
+
+#define MMUSUFFIX _mmu
+
+#define SHIFT 0
+#include "softmmu_template.h"
+
+#define SHIFT 1
+#include "softmmu_template.h"
+
+#define SHIFT 2
+#include "softmmu_template.h"
+
+#define SHIFT 3
+#include "softmmu_template.h"
+
+static void raise_exception(int tt)
+{
+ env->exception_index = tt;
+ cpu_loop_exit(env);
+}
+
+void tlb_fill(CPUUniCore32State *env1, target_ulong addr, int is_write, int mmu_idx,
+ uintptr_t retaddr)
+{
+ TranslationBlock *tb;
+ CPUUniCore32State *saved_env;
+ unsigned long pc;
+ int ret;
+
+ saved_env = env;
+ env = env1;
+ ret = uc32_cpu_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ if (unlikely(ret)) {
+ if (retaddr) {
+ /* now we have a real cpu fault */
+ pc = (unsigned long)retaddr;
+ tb = tb_find_pc(pc);
+ if (tb) {/* the PC is inside the translated code.
+ It means that we have a virtual CPU fault */
+ cpu_restore_state(tb, env, pc);
+ }
+ }
+ raise_exception(env->exception_index);
+ }
+ env = saved_env;
+}
+#endif
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 9793d14..d76fff0 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -176,6 +176,71 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
"Illegal UniCore32 instruction %x at line %d!", \
insn, __LINE__)
+#ifndef CONFIG_USER_ONLY
+static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
+{
+ TCGv tmp, tmp2, tmp3;
+ if ((insn & 0xfe000000) == 0xe0000000) {
+ tmp2 = new_tmp();
+ tmp3 = new_tmp();
+ tcg_gen_movi_i32(tmp2, UCOP_REG_N);
+ tcg_gen_movi_i32(tmp3, UCOP_IMM10);
+ if (UCOP_SET_L) {
+ tmp = new_tmp();
+ gen_helper_cp0_get(tmp, tmp2, tmp3);
+ store_reg(s, UCOP_REG_D, tmp);
+ } else {
+ tmp = load_reg(s, UCOP_REG_D);
+ gen_helper_cp0_set(tmp, tmp2, tmp3);
+ dead_tmp(tmp);
+ }
+ dead_tmp(tmp2);
+ dead_tmp(tmp3);
+ return;
+ }
+ ILLEGAL;
+}
+
+static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
+{
+ TCGv tmp;
+
+ if ((insn & 0xff003fff) == 0xe1000400) {
+ /*
+ * movc rd, pp.nn, #imm9
+ * rd: UCOP_REG_D
+ * nn: UCOP_REG_N (must be 0)
+ * imm9: 0
+ */
+ if (UCOP_REG_N == 0) {
+ tmp = new_tmp();
+ tcg_gen_movi_i32(tmp, 0);
+ store_reg(s, UCOP_REG_D, tmp);
+ return;
+ } else {
+ ILLEGAL;
+ }
+ }
+ if ((insn & 0xff003fff) == 0xe0000401) {
+ /*
+ * movc pp.nn, rn, #imm9
+ * rn: UCOP_REG_D
+ * nn: UCOP_REG_N (must be 1)
+ * imm9: 1
+ */
+ if (UCOP_REG_N == 1) {
+ tmp = load_reg(s, UCOP_REG_D);
+ gen_helper_cp1_putc(tmp);
+ dead_tmp(tmp);
+ return;
+ } else {
+ ILLEGAL;
+ }
+ }
+ ILLEGAL;
+}
+#endif
+
static inline void gen_set_asr(TCGv var, uint32_t mask)
{
TCGv tmp_mask = tcg_const_i32(mask);
@@ -1127,6 +1192,14 @@ static void gen_exception_return(DisasContext *s, TCGv pc)
static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
switch (UCOP_CPNUM) {
+#ifndef CONFIG_USER_ONLY
+ case 0:
+ disas_cp0_insn(env, s, insn);
+ break;
+ case 1:
+ disas_ocd_insn(env, s, insn);
+ break;
+#endif
case 2:
disas_ucf64_insn(env, s, insn);
break;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH 4/9] unicore32-softmmu: make sure that kernel can access user space
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
` (2 preceding siblings ...)
2012-05-25 11:29 ` [Qemu-devel] [PATCH 3/9] unicore32-softmmu: add coprocessor 0 and ocd instruction support Guan Xuetao
@ 2012-05-25 11:29 ` Guan Xuetao
2012-05-25 11:29 ` [Qemu-devel] [PATCH 5/9] unicore32-softmmu: initialize ucv2 cpu Guan Xuetao
` (6 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:29 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
target-unicore32/translate.c | 33 ++++++++++++++++++++++++---------
1 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index d76fff0..1f0ba4f 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -33,9 +33,16 @@ typedef struct DisasContext {
int condlabel;
struct TranslationBlock *tb;
int singlestep_enabled;
+#ifndef CONFIG_USER_ONLY
+ int user;
+#endif
} DisasContext;
+#ifndef CONFIG_USER_ONLY
+#define IS_USER(s) (s->user)
+#else
#define IS_USER(s) 1
+#endif
/* These instructions trap after executing, so defer them until after the
conditional executions state has been updated. */
@@ -1551,12 +1558,12 @@ static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* load/store I_offset and R_offset */
static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- unsigned int i;
+ unsigned int mmuindex;
TCGv tmp;
TCGv tmp2;
tmp2 = load_reg(s, UCOP_REG_N);
- i = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
+ mmuindex = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
/* immediate */
if (UCOP_SET_P) {
@@ -1566,17 +1573,17 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
if (UCOP_SET_L) {
/* load */
if (UCOP_SET_B) {
- tmp = gen_ld8u(tmp2, i);
+ tmp = gen_ld8u(tmp2, mmuindex);
} else {
- tmp = gen_ld32(tmp2, i);
+ tmp = gen_ld32(tmp2, mmuindex);
}
} else {
/* store */
tmp = load_reg(s, UCOP_REG_D);
if (UCOP_SET_B) {
- gen_st8(tmp, tmp2, i);
+ gen_st8(tmp, tmp2, mmuindex);
} else {
- gen_st32(tmp, tmp2, i);
+ gen_st32(tmp, tmp2, mmuindex);
}
}
if (!UCOP_SET_P) {
@@ -1679,7 +1686,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* load/store multiple words */
static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- unsigned int val, i;
+ unsigned int val, i, mmuindex;
int j, n, reg, user, loaded_base;
TCGv tmp;
TCGv tmp2;
@@ -1700,6 +1707,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
}
}
+ mmuindex = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W));
addr = load_reg(s, UCOP_REG_N);
/* compute total size */
@@ -1744,7 +1752,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
}
if (UCOP_SET(i)) {
if (UCOP_SET_L) { /* load */
- tmp = gen_ld32(addr, IS_USER(s));
+ tmp = gen_ld32(addr, mmuindex);
if (reg == 31) {
gen_bx(s, tmp);
} else if (user) {
@@ -1772,7 +1780,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
} else {
tmp = load_reg(s, reg);
}
- gen_st32(tmp, addr, IS_USER(s));
+ gen_st32(tmp, addr, mmuindex);
}
j++;
/* no need to add after the last transfer */
@@ -1953,6 +1961,13 @@ static inline void gen_intermediate_code_internal(CPUUniCore32State *env,
cpu_F1s = tcg_temp_new_i32();
cpu_F0d = tcg_temp_new_i64();
cpu_F1d = tcg_temp_new_i64();
+#ifndef CONFIG_USER_ONLY
+ if ((env->uncached_asr & 0x1f) == 0x10) {
+ dc->user = 1;
+ } else {
+ dc->user = 0;
+ }
+#endif
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
lj = -1;
num_insns = 0;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH 5/9] unicore32-softmmu: initialize ucv2 cpu
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
` (3 preceding siblings ...)
2012-05-25 11:29 ` [Qemu-devel] [PATCH 4/9] unicore32-softmmu: make sure that kernel can access user space Guan Xuetao
@ 2012-05-25 11:29 ` Guan Xuetao
2012-05-25 11:42 ` Andreas Färber
2012-05-25 11:29 ` [Qemu-devel] [PATCH 6/9] unicore32-softmmu: add generic cpu state save/load functions Guan Xuetao
` (5 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:29 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
target-unicore32/cpu.c | 17 +++++++++++++----
target-unicore32/cpu.h | 2 +-
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index de63f58..62c0a22 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -32,13 +32,16 @@ static void unicore_ii_cpu_initfn(Object *obj)
UniCore32CPU *cpu = UNICORE32_CPU(obj);
CPUUniCore32State *env = &cpu->env;
- env->cp0.c0_cpuid = 0x40010863;
+ env->cp0.c0_cpuid = UC32_CPUID_UCV2;
+ env->cp0.c0_cachetype = 0x0d152152;
+ env->cp0.c1_sys = 0x2000;
+ env->cp0.c2_base = 0x0;
+ env->cp0.c3_faultstatus = 0x0;
+ env->cp0.c4_faultaddr = 0x0;
+ env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
- env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
- env->cp0.c0_cachetype = 0x1dd20d2;
- env->cp0.c1_sys = 0x00090078;
}
static void uc32_any_cpu_initfn(Object *obj)
@@ -47,6 +50,7 @@ static void uc32_any_cpu_initfn(Object *obj)
CPUUniCore32State *env = &cpu->env;
env->cp0.c0_cpuid = 0xffffffff;
+ env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
set_feature(env, UC32_HWCAP_CMOV);
set_feature(env, UC32_HWCAP_UCF64);
@@ -65,8 +69,13 @@ static void uc32_cpu_initfn(Object *obj)
cpu_exec_init(env);
env->cpu_model_str = object_get_typename(obj);
+#ifdef CONFIG_USER_ONLY
env->uncached_asr = ASR_MODE_USER;
env->regs[31] = 0;
+#else
+ env->uncached_asr = ASR_MODE_PRIV;
+ env->regs[31] = 0x03000000;
+#endif
tlb_flush(env, 1);
}
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 66c42f5..8af3649 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -123,7 +123,7 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
#define UC32_HWCAP_UCF64 8 /* 1 << 3 */
#define UC32_CPUID(env) (env->cp0.c0_cpuid)
-#define UC32_CPUID_UCV2 0x40010863
+#define UC32_CPUID_UCV2 0x4d000863
#define UC32_CPUID_ANY 0xffffffff
#define cpu_init uc32_cpu_init
--
1.7.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH 5/9] unicore32-softmmu: initialize ucv2 cpu
2012-05-25 11:29 ` [Qemu-devel] [PATCH 5/9] unicore32-softmmu: initialize ucv2 cpu Guan Xuetao
@ 2012-05-25 11:42 ` Andreas Färber
2012-05-28 9:43 ` guanxuetao
0 siblings, 1 reply; 23+ messages in thread
From: Andreas Färber @ 2012-05-25 11:42 UTC (permalink / raw)
To: Guan Xuetao; +Cc: blauwirbel, qemu-devel
Am 25.05.2012 13:29, schrieb Guan Xuetao:
> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
> ---
> target-unicore32/cpu.c | 17 +++++++++++++----
> target-unicore32/cpu.h | 2 +-
> 2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> index de63f58..62c0a22 100644
> --- a/target-unicore32/cpu.c
> +++ b/target-unicore32/cpu.c
> @@ -32,13 +32,16 @@ static void unicore_ii_cpu_initfn(Object *obj)
> UniCore32CPU *cpu = UNICORE32_CPU(obj);
> CPUUniCore32State *env = &cpu->env;
>
> - env->cp0.c0_cpuid = 0x40010863;
> + env->cp0.c0_cpuid = UC32_CPUID_UCV2;
Please don't revert this change. I'll send you the patch to drop the
CPUID #defines instead.
Andreas
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index 66c42f5..8af3649 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -123,7 +123,7 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
> #define UC32_HWCAP_UCF64 8 /* 1 << 3 */
>
> #define UC32_CPUID(env) (env->cp0.c0_cpuid)
> -#define UC32_CPUID_UCV2 0x40010863
> +#define UC32_CPUID_UCV2 0x4d000863
> #define UC32_CPUID_ANY 0xffffffff
>
> #define cpu_init uc32_cpu_init
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 5/9] unicore32-softmmu: initialize ucv2 cpu
2012-05-25 11:42 ` Andreas Färber
@ 2012-05-28 9:43 ` guanxuetao
2012-05-28 13:14 ` Andreas Färber
0 siblings, 1 reply; 23+ messages in thread
From: guanxuetao @ 2012-05-28 9:43 UTC (permalink / raw)
To: Andreas F�rber; +Cc: blauwirbel, Guan Xuetao, qemu-devel
> Am 25.05.2012 13:29, schrieb Guan Xuetao:
>> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
>> ---
>> target-unicore32/cpu.c | 17 +++++++++++++----
>> target-unicore32/cpu.h | 2 +-
>> 2 files changed, 14 insertions(+), 5 deletions(-)
>>
>> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
>> index de63f58..62c0a22 100644
>> --- a/target-unicore32/cpu.c
>> +++ b/target-unicore32/cpu.c
>> @@ -32,13 +32,16 @@ static void unicore_ii_cpu_initfn(Object *obj)
>> UniCore32CPU *cpu = UNICORE32_CPU(obj);
>> CPUUniCore32State *env = &cpu->env;
>>
>> - env->cp0.c0_cpuid = 0x40010863;
>> + env->cp0.c0_cpuid = UC32_CPUID_UCV2;
>
> Please don't revert this change. I'll send you the patch to drop the
> CPUID #defines instead.
But, the kernel need this CPUID to check whether it is a unicore32
processor, and if check fail, the kernel will halt.
Guan Xuetao
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 5/9] unicore32-softmmu: initialize ucv2 cpu
2012-05-28 9:43 ` guanxuetao
@ 2012-05-28 13:14 ` Andreas Färber
0 siblings, 0 replies; 23+ messages in thread
From: Andreas Färber @ 2012-05-28 13:14 UTC (permalink / raw)
To: guanxuetao; +Cc: blauwirbel, Guan Xuetao, qemu-devel
Am 28.05.2012 11:43, schrieb guanxuetao@mprc.pku.edu.cn:
>> Am 25.05.2012 13:29, schrieb Guan Xuetao:
>>> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
>>> ---
>>> target-unicore32/cpu.c | 17 +++++++++++++----
>>> target-unicore32/cpu.h | 2 +-
>>> 2 files changed, 14 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
>>> index de63f58..62c0a22 100644
>>> --- a/target-unicore32/cpu.c
>>> +++ b/target-unicore32/cpu.c
>>> @@ -32,13 +32,16 @@ static void unicore_ii_cpu_initfn(Object *obj)
>>> UniCore32CPU *cpu = UNICORE32_CPU(obj);
>>> CPUUniCore32State *env = &cpu->env;
>>>
>>> - env->cp0.c0_cpuid = 0x40010863;
>>> + env->cp0.c0_cpuid = UC32_CPUID_UCV2;
>>
>> Please don't revert this change. I'll send you the patch to drop the
>> CPUID #defines instead.
>
> But, the kernel need this CPUID to check whether it is a unicore32
> processor, and if check fail, the kernel will halt.
I'm not discussing about a guest kernel but about your source change
above: The UC32_CPUID_UC32 #define should go away, i.e. please ack
(today, if we want it in 1.1) and prepend my patch, and if the value is
wrong here it should be changed *here* and not in UC32_CPUID_UCV2.
If you're introducing new uses of UC32_CPUID_UCV2 elsewhere (e.g., for
register behavior) then that is a design fault and needs to be fixed.
Compare the copro series for target-arm, which gets rid of the
CPUID-based switches there.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 6/9] unicore32-softmmu: add generic cpu state save/load functions
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
` (4 preceding siblings ...)
2012-05-25 11:29 ` [Qemu-devel] [PATCH 5/9] unicore32-softmmu: initialize ucv2 cpu Guan Xuetao
@ 2012-05-25 11:29 ` Guan Xuetao
2012-05-25 11:44 ` Andreas Färber
2012-05-25 11:45 ` 陳韋任
2012-05-25 11:29 ` [Qemu-devel] [PATCH 7/9] unicore32-softmmu: add puv3 soc support Guan Xuetao
` (4 subsequent siblings)
10 siblings, 2 replies; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:29 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
This patch adds generic cpu state save/load functions for UniCore32 ISA.
All architecture related registers are saved or loaded, and no optimization.
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
target-unicore32/machine.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 99 insertions(+), 0 deletions(-)
create mode 100644 target-unicore32/machine.c
diff --git a/target-unicore32/machine.c b/target-unicore32/machine.c
new file mode 100644
index 0000000..e8c52cd
--- /dev/null
+++ b/target-unicore32/machine.c
@@ -0,0 +1,99 @@
+/*
+ * Generic machine functions for UniCore32 ISA
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "hw/hw.h"
+
+void cpu_save(QEMUFile *f, void *opaque)
+{
+ int i;
+ CPUUniCore32State *env = (CPUUniCore32State *)opaque;
+
+ for (i = 0; i < 32; i++) {
+ qemu_put_be32(f, env->regs[i]);
+ }
+ qemu_put_be32(f, cpu_asr_read(env));
+ qemu_put_be32(f, env->bsr);
+ for (i = 0; i < 6; i++) {
+ qemu_put_be32(f, env->banked_bsr[i]);
+ qemu_put_be32(f, env->banked_r29[i]);
+ qemu_put_be32(f, env->banked_r30[i]);
+ }
+
+ qemu_put_be32(f, env->cp0.c0_cpuid);
+ qemu_put_be32(f, env->cp0.c0_cachetype);
+ qemu_put_be32(f, env->cp0.c1_sys);
+ qemu_put_be32(f, env->cp0.c2_base);
+ qemu_put_be32(f, env->cp0.c3_faultstatus);
+ qemu_put_be32(f, env->cp0.c4_faultaddr);
+ qemu_put_be32(f, env->cp0.c5_cacheop);
+ qemu_put_be32(f, env->cp0.c6_tlbop);
+
+ qemu_put_be32(f, env->features);
+
+ if (env->features & UC32_HWCAP_UCF64) {
+ for (i = 0; i < 16; i++) {
+ CPU_DoubleU u;
+ u.d = env->ucf64.regs[i];
+ qemu_put_be32(f, u.l.upper);
+ qemu_put_be32(f, u.l.lower);
+ }
+ for (i = 0; i < 32; i++) {
+ qemu_put_be32(f, env->ucf64.xregs[i]);
+ }
+ }
+}
+
+int cpu_load(QEMUFile *f, void *opaque, int version_id)
+{
+ CPUUniCore32State *env = (CPUUniCore32State *)opaque;
+ int i;
+ uint32_t val;
+
+ if (version_id != CPU_SAVE_VERSION) {
+ return -EINVAL;
+ }
+
+ for (i = 0; i < 32; i++) {
+ env->regs[i] = qemu_get_be32(f);
+ }
+ val = qemu_get_be32(f);
+ /* Avoid mode switch when restoring ASR. */
+ env->uncached_asr = val & ASR_M;
+ cpu_asr_write(env, val, 0xffffffff);
+ env->bsr = qemu_get_be32(f);
+ for (i = 0; i < 6; i++) {
+ env->banked_bsr[i] = qemu_get_be32(f);
+ env->banked_r29[i] = qemu_get_be32(f);
+ env->banked_r30[i] = qemu_get_be32(f);
+ }
+
+ env->cp0.c0_cpuid = qemu_get_be32(f);
+ env->cp0.c0_cachetype = qemu_get_be32(f);
+ env->cp0.c1_sys = qemu_get_be32(f);
+ env->cp0.c2_base = qemu_get_be32(f);
+ env->cp0.c3_faultstatus = qemu_get_be32(f);
+ env->cp0.c4_faultaddr = qemu_get_be32(f);
+ env->cp0.c5_cacheop = qemu_get_be32(f);
+ env->cp0.c6_tlbop = qemu_get_be32(f);
+
+ if (env->features & UC32_HWCAP_UCF64) {
+ for (i = 0; i < 16; i++) {
+ CPU_DoubleU u;
+ u.l.upper = qemu_get_be32(f);
+ u.l.lower = qemu_get_be32(f);
+ env->ucf64.regs[i] = u.d;
+ }
+ for (i = 0; i < 16; i++) {
+ env->ucf64.xregs[i] = qemu_get_be32(f);
+ }
+ }
+
+ return 0;
+}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH 6/9] unicore32-softmmu: add generic cpu state save/load functions
2012-05-25 11:29 ` [Qemu-devel] [PATCH 6/9] unicore32-softmmu: add generic cpu state save/load functions Guan Xuetao
@ 2012-05-25 11:44 ` Andreas Färber
2012-05-28 9:45 ` guanxuetao
2012-05-25 11:45 ` 陳韋任
1 sibling, 1 reply; 23+ messages in thread
From: Andreas Färber @ 2012-05-25 11:44 UTC (permalink / raw)
To: Guan Xuetao; +Cc: blauwirbel, qemu-devel
Am 25.05.2012 13:29, schrieb Guan Xuetao:
> This patch adds generic cpu state save/load functions for UniCore32 ISA.
> All architecture related registers are saved or loaded, and no optimization.
>
> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
> ---
> target-unicore32/machine.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 99 insertions(+), 0 deletions(-)
> create mode 100644 target-unicore32/machine.c
>
> diff --git a/target-unicore32/machine.c b/target-unicore32/machine.c
> new file mode 100644
> index 0000000..e8c52cd
> --- /dev/null
> +++ b/target-unicore32/machine.c
> @@ -0,0 +1,99 @@
> +/*
> + * Generic machine functions for UniCore32 ISA
> + *
> + * Copyright (C) 2010-2012 Guan Xuetao
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation, or any later version.
> + * See the COPYING file in the top-level directory.
> + */
> +#include "hw/hw.h"
> +
> +void cpu_save(QEMUFile *f, void *opaque)
> +{
> + int i;
> + CPUUniCore32State *env = (CPUUniCore32State *)opaque;
> +
> + for (i = 0; i < 32; i++) {
> + qemu_put_be32(f, env->regs[i]);
> + }
> + qemu_put_be32(f, cpu_asr_read(env));
> + qemu_put_be32(f, env->bsr);
[snip]
Please use VMState instead.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH 6/9] unicore32-softmmu: add generic cpu state save/load functions
2012-05-25 11:44 ` Andreas Färber
@ 2012-05-28 9:45 ` guanxuetao
0 siblings, 0 replies; 23+ messages in thread
From: guanxuetao @ 2012-05-28 9:45 UTC (permalink / raw)
To: Andreas F�rber; +Cc: blauwirbel, Guan Xuetao, qemu-devel
> Am 25.05.2012 13:29, schrieb Guan Xuetao:
>> This patch adds generic cpu state save/load functions for UniCore32 ISA.
>> All architecture related registers are saved or loaded, and no
>> optimization.
>>
>> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
>> ---
>> target-unicore32/machine.c | 99
>> ++++++++++++++++++++++++++++++++++++++++++++
>> 1 files changed, 99 insertions(+), 0 deletions(-)
>> create mode 100644 target-unicore32/machine.c
>>
>> diff --git a/target-unicore32/machine.c b/target-unicore32/machine.c
>> new file mode 100644
>> index 0000000..e8c52cd
>> --- /dev/null
>> +++ b/target-unicore32/machine.c
>> @@ -0,0 +1,99 @@
>> +/*
>> + * Generic machine functions for UniCore32 ISA
>> + *
>> + * Copyright (C) 2010-2012 Guan Xuetao
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation, or any later version.
>> + * See the COPYING file in the top-level directory.
>> + */
>> +#include "hw/hw.h"
>> +
>> +void cpu_save(QEMUFile *f, void *opaque)
>> +{
>> + int i;
>> + CPUUniCore32State *env = (CPUUniCore32State *)opaque;
>> +
>> + for (i = 0; i < 32; i++) {
>> + qemu_put_be32(f, env->regs[i]);
>> + }
>> + qemu_put_be32(f, cpu_asr_read(env));
>> + qemu_put_be32(f, env->bsr);
> [snip]
>
> Please use VMState instead.
>
> Andreas
Thanks, I will try it.
Guan Xuetao
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 6/9] unicore32-softmmu: add generic cpu state save/load functions
2012-05-25 11:29 ` [Qemu-devel] [PATCH 6/9] unicore32-softmmu: add generic cpu state save/load functions Guan Xuetao
2012-05-25 11:44 ` Andreas Färber
@ 2012-05-25 11:45 ` 陳韋任
1 sibling, 0 replies; 23+ messages in thread
From: 陳韋任 @ 2012-05-25 11:45 UTC (permalink / raw)
To: Guan Xuetao; +Cc: blauwirbel, qemu-devel
Hi Guan,
> +void cpu_save(QEMUFile *f, void *opaque)
> +{
> + int i;
> + CPUUniCore32State *env = (CPUUniCore32State *)opaque;
> +
> + for (i = 0; i < 32; i++) {
> + qemu_put_be32(f, env->regs[i]);
> + }
> + qemu_put_be32(f, cpu_asr_read(env));
> + qemu_put_be32(f, env->bsr);
> + for (i = 0; i < 6; i++) {
> + qemu_put_be32(f, env->banked_bsr[i]);
> + qemu_put_be32(f, env->banked_r29[i]);
> + qemu_put_be32(f, env->banked_r30[i]);
> + }
> +
> + qemu_put_be32(f, env->cp0.c0_cpuid);
> + qemu_put_be32(f, env->cp0.c0_cachetype);
> + qemu_put_be32(f, env->cp0.c1_sys);
> + qemu_put_be32(f, env->cp0.c2_base);
> + qemu_put_be32(f, env->cp0.c3_faultstatus);
> + qemu_put_be32(f, env->cp0.c4_faultaddr);
> + qemu_put_be32(f, env->cp0.c5_cacheop);
> + qemu_put_be32(f, env->cp0.c6_tlbop);
> +
> + qemu_put_be32(f, env->features);
> +
> + if (env->features & UC32_HWCAP_UCF64) {
> + for (i = 0; i < 16; i++) {
> + CPU_DoubleU u;
> + u.d = env->ucf64.regs[i];
> + qemu_put_be32(f, u.l.upper);
> + qemu_put_be32(f, u.l.lower);
> + }
> + for (i = 0; i < 32; i++) {
> + qemu_put_be32(f, env->ucf64.xregs[i]);
> + }
> + }
> +}
Do you think use VMState rather then QEMUFile is a good idea?
I saw OpenRISC target got this kind of feedback before [1].
Regards,
chenwj
[1] http://lists.gnu.org/archive/html/qemu-devel/2012-05/msg02457.html
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 7/9] unicore32-softmmu: add puv3 soc support
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
` (5 preceding siblings ...)
2012-05-25 11:29 ` [Qemu-devel] [PATCH 6/9] unicore32-softmmu: add generic cpu state save/load functions Guan Xuetao
@ 2012-05-25 11:29 ` Guan Xuetao
2012-05-25 11:46 ` Andreas Färber
2012-05-25 11:29 ` [Qemu-devel] [PATCH 8/9] unicore32-softmmu: add config and makefile support Guan Xuetao
` (3 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:29 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
This patch only add minimal necessary system-control modules simulation
for successfully kernel booting and busybox running.
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
hw/pkunity/puv3.c | 130 +++++++++++++++++++++++++++++++++++++++++
hw/pkunity/puv3.h | 49 ++++++++++++++++
hw/pkunity/puv3_dma.c | 109 ++++++++++++++++++++++++++++++++++
hw/pkunity/puv3_gpio.c | 141 ++++++++++++++++++++++++++++++++++++++++++++
hw/pkunity/puv3_intc.c | 135 ++++++++++++++++++++++++++++++++++++++++++
hw/pkunity/puv3_ost.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++
hw/pkunity/puv3_pm.c | 148 +++++++++++++++++++++++++++++++++++++++++++++++
7 files changed, 863 insertions(+), 0 deletions(-)
create mode 100644 hw/pkunity/puv3.c
create mode 100644 hw/pkunity/puv3.h
create mode 100644 hw/pkunity/puv3_dma.c
create mode 100644 hw/pkunity/puv3_gpio.c
create mode 100644 hw/pkunity/puv3_intc.c
create mode 100644 hw/pkunity/puv3_ost.c
create mode 100644 hw/pkunity/puv3_pm.c
diff --git a/hw/pkunity/puv3.c b/hw/pkunity/puv3.c
new file mode 100644
index 0000000..2e18f71
--- /dev/null
+++ b/hw/pkunity/puv3.c
@@ -0,0 +1,130 @@
+/*
+ * Generic PKUnity SoC machine and board descriptor
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "console.h"
+#include "elf.h"
+#include "exec-memory.h"
+#include "../sysbus.h"
+#include "../boards.h"
+#include "../loader.h"
+#include "../pc.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+#define KERNEL_LOAD_ADDR 0x03000000
+#define KERNEL_MAX_SIZE 0x00800000 /* Just a guess */
+
+static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
+{
+ CPUUniCore32State *env = (CPUUniCore32State *)opaque;
+
+ assert(irq == 0);
+ if (level) {
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ }
+}
+
+static void puv3_soc_init(CPUUniCore32State *env)
+{
+ qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
+ DeviceState *dev;
+ MemoryRegion *i8042 = g_new(MemoryRegion, 1);
+ int i;
+
+ /* Initialize interrupt controller */
+ cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);
+ dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);
+ for (i = 0; i < PUV3_IRQS_NR; i++) {
+ irqs[i] = qdev_get_gpio_in(dev, i);
+ }
+
+ /* Initialize minimal necessary devices for kernel booting */
+ sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);
+ sysbus_create_simple("puv3_dma", PUV3_DMA_BASE, NULL);
+ sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
+ sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
+ irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
+ irqs[PUV3_IRQS_GPIOLOW2], irqs[PUV3_IRQS_GPIOLOW3],
+ irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],
+ irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],
+ irqs[PUV3_IRQS_GPIOHIGH], NULL);
+
+ /* Keyboard (i8042), mouse disabled for nographic */
+ i8042_mm_init(irqs[PUV3_IRQS_PS2_KBD], NULL, i8042, PUV3_REGS_OFFSET, 4);
+ memory_region_add_subregion(get_system_memory(), PUV3_PS2_BASE, i8042);
+}
+
+static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
+{
+ MemoryRegion *ram_memory = g_new(MemoryRegion, 1);
+
+ /* SDRAM at address zero. */
+ memory_region_init_ram(ram_memory, "puv3.ram", ram_size);
+ vmstate_register_ram_global(ram_memory);
+ memory_region_add_subregion(get_system_memory(), 0, ram_memory);
+}
+
+static void puv3_load_kernel(const char *kernel_filename)
+{
+ int size;
+
+ assert(kernel_filename != NULL);
+
+ /* only zImage format supported */
+ size = load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR,
+ KERNEL_MAX_SIZE);
+ if (size < 0) {
+ hw_error("Load kernel error: '%s'\n", kernel_filename);
+ }
+
+ /* cheat curses that we have a graphic console, only under ocd console */
+ graphic_console_init(NULL, NULL, NULL, NULL, NULL);
+}
+
+static void puv3_init(ram_addr_t ram_size, const char *boot_device,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ CPUUniCore32State *env;
+
+ if (initrd_filename) {
+ hw_error("Please use kernel built-in initramdisk.\n");
+ }
+
+ if (!cpu_model) {
+ cpu_model = "UniCore-II";
+ }
+
+ env = cpu_init(cpu_model);
+ if (!env) {
+ hw_error("Unable to find CPU definition\n");
+ }
+
+ puv3_soc_init(env);
+ puv3_board_init(env, ram_size);
+ puv3_load_kernel(kernel_filename);
+}
+
+static QEMUMachine puv3_machine = {
+ .name = "puv3",
+ .desc = "PKUnity Version-3 based on UniCore32",
+ .init = puv3_init,
+ .use_scsi = 0,
+};
+
+static void puv3_machine_init(void)
+{
+ qemu_register_machine(&puv3_machine);
+}
+
+machine_init(puv3_machine_init);
diff --git a/hw/pkunity/puv3.h b/hw/pkunity/puv3.h
new file mode 100644
index 0000000..9d1018a
--- /dev/null
+++ b/hw/pkunity/puv3.h
@@ -0,0 +1,49 @@
+/*
+ * Misc PKUnity SoC declarations
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#ifndef __PUV3_H__
+#define __PUV3_H__
+
+#define PUV3_REGS_OFFSET (TARGET_PAGE_SIZE)
+
+/* PKUnity System bus (AHB): 0xc0000000 - 0xedffffff (640MB) */
+#define PUV3_DMA_BASE (0xc0200000) /* AHB-4 */
+
+/* PKUnity Peripheral bus (APB): 0xee000000 - 0xefffffff (128MB) */
+#define PUV3_GPIO_BASE (0xee500000) /* APB-5 */
+#define PUV3_INTC_BASE (0xee600000) /* APB-6 */
+#define PUV3_OST_BASE (0xee800000) /* APB-8 */
+#define PUV3_PM_BASE (0xeea00000) /* APB-10 */
+#define PUV3_PS2_BASE (0xeeb00000) /* APB-11 */
+
+/* Hardware interrupts */
+#define PUV3_IRQS_NR (32)
+
+#define PUV3_IRQS_GPIOLOW0 (0)
+#define PUV3_IRQS_GPIOLOW1 (1)
+#define PUV3_IRQS_GPIOLOW2 (2)
+#define PUV3_IRQS_GPIOLOW3 (3)
+#define PUV3_IRQS_GPIOLOW4 (4)
+#define PUV3_IRQS_GPIOLOW5 (5)
+#define PUV3_IRQS_GPIOLOW6 (6)
+#define PUV3_IRQS_GPIOLOW7 (7)
+#define PUV3_IRQS_GPIOHIGH (8)
+#define PUV3_IRQS_PS2_KBD (22)
+#define PUV3_IRQS_PS2_AUX (23)
+#define PUV3_IRQS_OST0 (26)
+
+/* All puv3_*.c use DPRINTF for debug. */
+#ifdef DEBUG_PUV3
+#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+#endif /* !__PUV3_H__ */
diff --git a/hw/pkunity/puv3_dma.c b/hw/pkunity/puv3_dma.c
new file mode 100644
index 0000000..07e9908
--- /dev/null
+++ b/hw/pkunity/puv3_dma.c
@@ -0,0 +1,109 @@
+/*
+ * DMA device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "../hw.h"
+#include "../sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+#define PUV3_DMA_CH_NR (6)
+#define PUV3_DMA_CH_MASK (0xff)
+#define PUV3_DMA_CH(offset) ((offset) >> 8)
+
+typedef struct {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
+ uint32_t reg_CFG[PUV3_DMA_CH_NR];
+} puv3_dma_t;
+
+static uint64_t puv3_dma_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
+{
+ puv3_dma_t *s = (puv3_dma_t *) opaque;
+ uint32_t ret;
+
+ assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
+
+ switch (offset & PUV3_DMA_CH_MASK) {
+ case 0x10:
+ ret = s->reg_CFG[PUV3_DMA_CH(offset)];
+ break;
+ default:
+ hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+ }
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+ return ret;
+}
+
+static void puv3_dma_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
+{
+ puv3_dma_t *s = (puv3_dma_t *) opaque;
+
+ assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
+
+ switch (offset & PUV3_DMA_CH_MASK) {
+ case 0x10:
+ s->reg_CFG[PUV3_DMA_CH(offset)] = value;
+ break;
+ default:
+ hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+ }
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+}
+
+static const MemoryRegionOps puv3_dma_ops = {
+ .read = puv3_dma_read,
+ .write = puv3_dma_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_dma_init(SysBusDevice *dev)
+{
+ puv3_dma_t *s = FROM_SYSBUS(puv3_dma_t, dev);
+ int i;
+
+ for (i = 0; i < PUV3_DMA_CH_NR; i++) {
+ s->reg_CFG[i] = 0x0;
+ }
+
+ memory_region_init_io(&s->iomem, &puv3_dma_ops, s, "puv3_dma",
+ PUV3_REGS_OFFSET);
+ sysbus_init_mmio(dev, &s->iomem);
+
+ return 0;
+}
+
+static void puv3_dma_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = puv3_dma_init;
+}
+
+static TypeInfo puv3_dma_info = {
+ .name = "puv3_dma",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(puv3_dma_t),
+ .class_init = puv3_dma_class_init,
+};
+
+static void puv3_dma_register_type(void)
+{
+ type_register_static(&puv3_dma_info);
+}
+
+type_init(puv3_dma_register_type)
diff --git a/hw/pkunity/puv3_gpio.c b/hw/pkunity/puv3_gpio.c
new file mode 100644
index 0000000..01ed54e
--- /dev/null
+++ b/hw/pkunity/puv3_gpio.c
@@ -0,0 +1,141 @@
+/*
+ * GPIO device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "../hw.h"
+#include "../sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
+ qemu_irq irq[9];
+
+ uint32_t reg_GPLR;
+ uint32_t reg_GPDR;
+ uint32_t reg_GPIR;
+} puv3_gpio_t;
+
+static uint64_t puv3_gpio_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
+{
+ puv3_gpio_t *s = (puv3_gpio_t *) opaque;
+ uint32_t ret;
+
+ switch (offset) {
+ case 0x00:
+ ret = s->reg_GPLR;
+ break;
+ case 0x04:
+ ret = s->reg_GPDR;
+ break;
+ case 0x20:
+ ret = s->reg_GPIR;
+ break;
+ default:
+ hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+ }
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+ return ret;
+}
+
+static void puv3_gpio_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
+{
+ puv3_gpio_t *s = (puv3_gpio_t *) opaque;
+
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+ switch (offset) {
+ case 0x04:
+ s->reg_GPDR = value;
+ break;
+ case 0x08:
+ if (s->reg_GPDR & value) {
+ s->reg_GPLR |= value;
+ } else {
+ hw_error("write gpio input port error!");
+ }
+ break;
+ case 0x0c:
+ if (s->reg_GPDR & value) {
+ s->reg_GPLR &= ~value;
+ } else {
+ hw_error("write gpio input port error!");
+ }
+ break;
+ case 0x10: /* GRER */
+ case 0x14: /* GFER */
+ case 0x18: /* GEDR */
+ break;
+ case 0x20: /* GPIR */
+ s->reg_GPIR = value;
+ break;
+ default:
+ hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+ }
+}
+
+static const MemoryRegionOps puv3_gpio_ops = {
+ .read = puv3_gpio_read,
+ .write = puv3_gpio_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_gpio_init(SysBusDevice *dev)
+{
+ puv3_gpio_t *s = FROM_SYSBUS(puv3_gpio_t, dev);
+
+ s->reg_GPLR = 0;
+ s->reg_GPDR = 0;
+
+ /* FIXME: these irqs not handled yet */
+ sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]);
+ sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]);
+ sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]);
+ sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]);
+ sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]);
+ sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]);
+ sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]);
+ sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]);
+ sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]);
+
+ memory_region_init_io(&s->iomem, &puv3_gpio_ops, s, "puv3_gpio",
+ PUV3_REGS_OFFSET);
+ sysbus_init_mmio(dev, &s->iomem);
+
+ return 0;
+}
+
+static void puv3_gpio_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = puv3_gpio_init;
+}
+
+static TypeInfo puv3_gpio_info = {
+ .name = "puv3_gpio",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(puv3_gpio_t),
+ .class_init = puv3_gpio_class_init,
+};
+
+static void puv3_gpio_register_type(void)
+{
+ type_register_static(&puv3_gpio_info);
+}
+
+type_init(puv3_gpio_register_type)
diff --git a/hw/pkunity/puv3_intc.c b/hw/pkunity/puv3_intc.c
new file mode 100644
index 0000000..f40c42d
--- /dev/null
+++ b/hw/pkunity/puv3_intc.c
@@ -0,0 +1,135 @@
+/*
+ * INTC device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "../sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct puv3_intc_t {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
+ qemu_irq parent_irq;
+
+ uint32_t reg_ICMR;
+ uint32_t reg_ICPR;
+} puv3_intc_t;
+
+/* Update interrupt status after enabled or pending bits have been changed. */
+static void puv3_intc_update(puv3_intc_t *s)
+{
+ if (s->reg_ICMR & s->reg_ICPR) {
+ qemu_irq_raise(s->parent_irq);
+ } else {
+ qemu_irq_lower(s->parent_irq);
+ }
+}
+
+/* Process a change in an external INTC input. */
+static void puv3_intc_handler(void *opaque, int irq, int level)
+{
+ puv3_intc_t *s = (puv3_intc_t *)opaque;
+
+ DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
+ if (level) {
+ s->reg_ICPR |= (1 << irq);
+ } else {
+ s->reg_ICPR &= ~(1 << irq);
+ }
+ puv3_intc_update(s);
+}
+
+static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
+{
+ puv3_intc_t *s = (puv3_intc_t *)opaque;
+ uint32_t ret = 0;
+
+ switch (offset) {
+ case 0x04: /* INTC_ICMR */
+ ret = s->reg_ICMR;
+ break;
+ case 0x0c: /* INTC_ICIP */
+ ret = s->reg_ICPR; /* the same value with ICPR */
+ break;
+ default:
+ hw_error("puv3_intc_read: Bad offset %x\n", (int)offset);
+ }
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+ return ret;
+}
+
+static void puv3_intc_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
+{
+ puv3_intc_t *s = (puv3_intc_t *)opaque;
+
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+ switch (offset) {
+ case 0x00: /* INTC_ICLR */
+ case 0x14: /* INTC_ICCR */
+ break;
+ case 0x04: /* INTC_ICMR */
+ s->reg_ICMR = value;
+ break;
+ default:
+ hw_error("puv3_intc_write: Bad offset 0x%x\n", (int)offset);
+ return;
+ }
+ puv3_intc_update(s);
+}
+
+static const MemoryRegionOps puv3_intc_ops = {
+ .read = puv3_intc_read,
+ .write = puv3_intc_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_intc_init(SysBusDevice *dev)
+{
+ puv3_intc_t *s = FROM_SYSBUS(puv3_intc_t, dev);
+
+ qdev_init_gpio_in(&s->busdev.qdev, puv3_intc_handler, PUV3_IRQS_NR);
+ sysbus_init_irq(&s->busdev, &s->parent_irq);
+
+ s->reg_ICMR = 0;
+ s->reg_ICPR = 0;
+
+ memory_region_init_io(&s->iomem, &puv3_intc_ops, s, "puv3_intc",
+ PUV3_REGS_OFFSET);
+ sysbus_init_mmio(dev, &s->iomem);
+
+ return 0;
+}
+
+static void puv3_intc_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = puv3_intc_init;
+}
+
+static TypeInfo puv3_intc_info = {
+ .name = "puv3_intc",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(puv3_intc_t),
+ .class_init = puv3_intc_class_init,
+};
+
+static void puv3_intc_register_type(void)
+{
+ type_register_static(&puv3_intc_info);
+}
+
+type_init(puv3_intc_register_type)
diff --git a/hw/pkunity/puv3_ost.c b/hw/pkunity/puv3_ost.c
new file mode 100644
index 0000000..7f0fd3b
--- /dev/null
+++ b/hw/pkunity/puv3_ost.c
@@ -0,0 +1,151 @@
+/*
+ * OSTimer device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "../sysbus.h"
+#include "../ptimer.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+/* puv3 ostimer implementation. */
+typedef struct {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
+ QEMUBH *bh;
+ qemu_irq irq;
+ ptimer_state *ptimer;
+
+ uint32_t reg_OSMR0;
+ uint32_t reg_OSCR;
+ uint32_t reg_OSSR;
+ uint32_t reg_OIER;
+} puv3_ost_t;
+
+static uint64_t puv3_ost_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
+{
+ puv3_ost_t *s = (puv3_ost_t *)opaque;
+ uint32_t ret = 0;
+
+ switch (offset) {
+ case 0x10: /* Counter Register */
+ ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
+ break;
+ case 0x14: /* Status Register */
+ ret = s->reg_OSSR;
+ break;
+ case 0x1c: /* Interrupt Enable Register */
+ ret = s->reg_OIER;
+ break;
+ default:
+ hw_error("puv3_ost_read: Bad offset %x\n", (int)offset);
+ }
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+ return ret;
+}
+
+static void puv3_ost_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
+{
+ puv3_ost_t *s = (puv3_ost_t *)opaque;
+
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+ switch (offset) {
+ case 0x00: /* Match Register 0 */
+ s->reg_OSMR0 = value;
+ if (s->reg_OSMR0 > s->reg_OSCR) {
+ ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
+ } else {
+ ptimer_set_count(s->ptimer, s->reg_OSMR0 +
+ (0xffffffff - s->reg_OSCR));
+ }
+ ptimer_run(s->ptimer, 2);
+ break;
+ case 0x14: /* Status Register */
+ assert(value == 0);
+ if (s->reg_OSSR) {
+ s->reg_OSSR = value;
+ qemu_irq_lower(s->irq);
+ }
+ break;
+ case 0x1c: /* Interrupt Enable Register */
+ s->reg_OIER = value;
+ break;
+ default:
+ hw_error("puv3_ost_write: Bad offset %x\n", (int)offset);
+ }
+}
+
+static const MemoryRegionOps puv3_ost_ops = {
+ .read = puv3_ost_read,
+ .write = puv3_ost_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void puv3_ost_tick(void *opaque)
+{
+ puv3_ost_t *s = (puv3_ost_t *)opaque;
+
+ DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
+ s->reg_OSCR, s->reg_OSMR0);
+
+ s->reg_OSCR = s->reg_OSMR0;
+ if (s->reg_OIER) {
+ s->reg_OSSR = 1;
+ qemu_irq_raise(s->irq);
+ }
+}
+
+static int puv3_ost_init(SysBusDevice *dev)
+{
+ puv3_ost_t *s = FROM_SYSBUS(puv3_ost_t, dev);
+
+ s->reg_OIER = 0;
+ s->reg_OSSR = 0;
+ s->reg_OSMR0 = 0;
+ s->reg_OSCR = 0;
+
+ sysbus_init_irq(dev, &s->irq);
+
+ s->bh = qemu_bh_new(puv3_ost_tick, s);
+ s->ptimer = ptimer_init(s->bh);
+ ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
+
+ memory_region_init_io(&s->iomem, &puv3_ost_ops, s, "puv3_ost",
+ PUV3_REGS_OFFSET);
+ sysbus_init_mmio(dev, &s->iomem);
+
+ return 0;
+}
+
+static void puv3_ost_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = puv3_ost_init;
+}
+
+static TypeInfo puv3_ost_info = {
+ .name = "puv3_ost",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(puv3_ost_t),
+ .class_init = puv3_ost_class_init,
+};
+
+static void puv3_ost_register_type(void)
+{
+ type_register_static(&puv3_ost_info);
+}
+
+type_init(puv3_ost_register_type)
diff --git a/hw/pkunity/puv3_pm.c b/hw/pkunity/puv3_pm.c
new file mode 100644
index 0000000..1184105
--- /dev/null
+++ b/hw/pkunity/puv3_pm.c
@@ -0,0 +1,148 @@
+/*
+ * Power Management device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "../hw.h"
+#include "../sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
+
+ uint32_t reg_PMCR;
+ uint32_t reg_PCGR;
+ uint32_t reg_PLL_SYS_CFG;
+ uint32_t reg_PLL_DDR_CFG;
+ uint32_t reg_PLL_VGA_CFG;
+ uint32_t reg_DIVCFG;
+} puv3_pm_t;
+
+static uint64_t puv3_pm_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
+{
+ puv3_pm_t *s = (puv3_pm_t *) opaque;
+ uint32_t ret;
+
+ switch (offset) {
+ case 0x14:
+ ret = s->reg_PCGR;
+ break;
+ case 0x18:
+ ret = s->reg_PLL_SYS_CFG;
+ break;
+ case 0x1c:
+ ret = s->reg_PLL_DDR_CFG;
+ break;
+ case 0x20:
+ ret = s->reg_PLL_VGA_CFG;
+ break;
+ case 0x24:
+ ret = s->reg_DIVCFG;
+ break;
+ case 0x28: /* PLL SYS STATUS */
+ ret = 0x00002401;
+ break;
+ case 0x2c: /* PLL DDR STATUS */
+ ret = 0x00100c00;
+ break;
+ case 0x30: /* PLL VGA STATUS */
+ ret = 0x00003801;
+ break;
+ case 0x34: /* DIV STATUS */
+ ret = 0x22f52015;
+ break;
+ case 0x38: /* SW RESET */
+ ret = 0x0;
+ break;
+ case 0x44: /* PLL DFC DONE */
+ ret = 0x7;
+ break;
+ default:
+ hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+ }
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+
+ return ret;
+}
+
+static void puv3_pm_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
+{
+ puv3_pm_t *s = (puv3_pm_t *) opaque;
+
+ switch (offset) {
+ case 0x0:
+ s->reg_PMCR = value;
+ case 0x14:
+ s->reg_PCGR = value;
+ break;
+ case 0x18:
+ s->reg_PLL_SYS_CFG = value;
+ break;
+ case 0x1c:
+ s->reg_PLL_DDR_CFG = value;
+ break;
+ case 0x20:
+ s->reg_PLL_VGA_CFG = value;
+ break;
+ case 0x24:
+ case 0x38:
+ break;
+ default:
+ hw_error("%s: Bad offset 0x%x\n", __func__, offset);
+ }
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+}
+
+static const MemoryRegionOps puv3_pm_ops = {
+ .read = puv3_pm_read,
+ .write = puv3_pm_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_pm_init(SysBusDevice *dev)
+{
+ puv3_pm_t *s = FROM_SYSBUS(puv3_pm_t, dev);
+
+ s->reg_PCGR = 0x0;
+
+ memory_region_init_io(&s->iomem, &puv3_pm_ops, s, "puv3_pm",
+ PUV3_REGS_OFFSET);
+ sysbus_init_mmio(dev, &s->iomem);
+
+ return 0;
+}
+
+static void puv3_pm_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = puv3_pm_init;
+}
+
+static TypeInfo puv3_pm_info = {
+ .name = "puv3_pm",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(puv3_pm_t),
+ .class_init = puv3_pm_class_init,
+};
+
+static void puv3_pm_register_type(void)
+{
+ type_register_static(&puv3_pm_info);
+}
+
+type_init(puv3_pm_register_type)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH 7/9] unicore32-softmmu: add puv3 soc support
2012-05-25 11:29 ` [Qemu-devel] [PATCH 7/9] unicore32-softmmu: add puv3 soc support Guan Xuetao
@ 2012-05-25 11:46 ` Andreas Färber
2012-05-28 9:58 ` guanxuetao
0 siblings, 1 reply; 23+ messages in thread
From: Andreas Färber @ 2012-05-25 11:46 UTC (permalink / raw)
To: Guan Xuetao; +Cc: blauwirbel, qemu-devel
Am 25.05.2012 13:29, schrieb Guan Xuetao:
> This patch only add minimal necessary system-control modules simulation
> for successfully kernel booting and busybox running.
>
> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
> ---
> hw/pkunity/puv3.c | 130 +++++++++++++++++++++++++++++++++++++++++
> hw/pkunity/puv3.h | 49 ++++++++++++++++
> hw/pkunity/puv3_dma.c | 109 ++++++++++++++++++++++++++++++++++
> hw/pkunity/puv3_gpio.c | 141 ++++++++++++++++++++++++++++++++++++++++++++
> hw/pkunity/puv3_intc.c | 135 ++++++++++++++++++++++++++++++++++++++++++
> hw/pkunity/puv3_ost.c | 151 ++++++++++++++++++++++++++++++++++++++++++++++++
> hw/pkunity/puv3_pm.c | 148 +++++++++++++++++++++++++++++++++++++++++++++++
> 7 files changed, 863 insertions(+), 0 deletions(-)
> create mode 100644 hw/pkunity/puv3.c
> create mode 100644 hw/pkunity/puv3.h
> create mode 100644 hw/pkunity/puv3_dma.c
> create mode 100644 hw/pkunity/puv3_gpio.c
> create mode 100644 hw/pkunity/puv3_intc.c
> create mode 100644 hw/pkunity/puv3_ost.c
> create mode 100644 hw/pkunity/puv3_pm.c
Added a subdirectory without adapting configure and possibly Makefiles
will break out-of-tree builds. Can't you just name the files
puv3_something.[ch] as done for other SoCs?
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 7/9] unicore32-softmmu: add puv3 soc support
2012-05-25 11:46 ` Andreas Färber
@ 2012-05-28 9:58 ` guanxuetao
0 siblings, 0 replies; 23+ messages in thread
From: guanxuetao @ 2012-05-28 9:58 UTC (permalink / raw)
To: Andreas F�rber; +Cc: blauwirbel, Guan Xuetao, qemu-devel
> Am 25.05.2012 13:29, schrieb Guan Xuetao:
>> This patch only add minimal necessary system-control modules simulation
>> for successfully kernel booting and busybox running.
>>
>> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
>> ---
>> hw/pkunity/puv3.c | 130 +++++++++++++++++++++++++++++++++++++++++
>> hw/pkunity/puv3.h | 49 ++++++++++++++++
>> hw/pkunity/puv3_dma.c | 109 ++++++++++++++++++++++++++++++++++
>> hw/pkunity/puv3_gpio.c | 141
>> ++++++++++++++++++++++++++++++++++++++++++++
>> hw/pkunity/puv3_intc.c | 135
>> ++++++++++++++++++++++++++++++++++++++++++
>> hw/pkunity/puv3_ost.c | 151
>> ++++++++++++++++++++++++++++++++++++++++++++++++
>> hw/pkunity/puv3_pm.c | 148
>> +++++++++++++++++++++++++++++++++++++++++++++++
>> 7 files changed, 863 insertions(+), 0 deletions(-)
>> create mode 100644 hw/pkunity/puv3.c
>> create mode 100644 hw/pkunity/puv3.h
>> create mode 100644 hw/pkunity/puv3_dma.c
>> create mode 100644 hw/pkunity/puv3_gpio.c
>> create mode 100644 hw/pkunity/puv3_intc.c
>> create mode 100644 hw/pkunity/puv3_ost.c
>> create mode 100644 hw/pkunity/puv3_pm.c
>
> Added a subdirectory without adapting configure and possibly Makefiles
> will break out-of-tree builds. Can't you just name the files
> puv3_something.[ch] as done for other SoCs?
>
> Andreas
>
Every time, when I 'ls' the source tree of qemu or qemu/hw, it will
generate a terrible and over-one-screen output. So, I think a new
subdirectory makes it more clear (well-organized) and effective.
Guan Xuetao
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 8/9] unicore32-softmmu: add config and makefile support
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
` (6 preceding siblings ...)
2012-05-25 11:29 ` [Qemu-devel] [PATCH 7/9] unicore32-softmmu: add puv3 soc support Guan Xuetao
@ 2012-05-25 11:29 ` Guan Xuetao
2012-05-25 11:48 ` Andreas Färber
2012-05-25 11:29 ` [Qemu-devel] [PATCH 9/9] unicore32-softmmu: add maintainer information Guan Xuetao
` (2 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:29 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
This patch adds configure and makefile support for unicore32-softmmu.
All puv3-soc devices are put into hw/pkunity directory, so this dir
will be added when unicore32-softmmu is selected.
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
Makefile.target | 5 +++++
arch_init.c | 2 ++
arch_init.h | 1 +
configure | 4 ++++
default-configs/unicore32-softmmu.mak | 4 ++++
5 files changed, 16 insertions(+), 0 deletions(-)
create mode 100644 default-configs/unicore32-softmmu.mak
diff --git a/Makefile.target b/Makefile.target
index 1582904..2f850d3 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -387,6 +387,11 @@ obj-xtensa-y += core-dc232b.o
obj-xtensa-y += core-dc233c.o
obj-xtensa-y += core-fsf.o
+obj-unicore32-y += uc32_softmmu.o
+obj-unicore32-y += pkunity/puv3.o
+obj-unicore32-y += pkunity/puv3_intc.o pkunity/puv3_ost.o pkunity/puv3_gpio.o
+obj-unicore32-y += pkunity/puv3_pm.o pkunity/puv3_dma.o
+
main.o: QEMU_CFLAGS+=$(GPROF_CFLAGS)
monitor.o: hmp-commands.h qmp-commands-old.h
diff --git a/arch_init.c b/arch_init.c
index 988adca..9314025 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -81,6 +81,8 @@ int graphic_depth = 15;
#define QEMU_ARCH QEMU_ARCH_SPARC
#elif defined(TARGET_XTENSA)
#define QEMU_ARCH QEMU_ARCH_XTENSA
+#elif defined(TARGET_UNICORE32)
+#define QEMU_ARCH QEMU_ARCH_UNICORE32
#endif
const uint32_t arch_type = QEMU_ARCH;
diff --git a/arch_init.h b/arch_init.h
index c7cb94a..5298139 100644
--- a/arch_init.h
+++ b/arch_init.h
@@ -16,6 +16,7 @@ enum {
QEMU_ARCH_SH4 = 1024,
QEMU_ARCH_SPARC = 2048,
QEMU_ARCH_XTENSA = 4096,
+ QEMU_ARCH_UNICORE32 = 8192,
};
extern const uint32_t arch_type;
diff --git a/configure b/configure
index b55a792..e4a7c3a 100755
--- a/configure
+++ b/configure
@@ -934,6 +934,7 @@ sparc64-softmmu \
s390x-softmmu \
xtensa-softmmu \
xtensaeb-softmmu \
+unicore32-softmmu \
"
fi
# the following are Linux specific
@@ -3504,6 +3505,9 @@ mkdir -p $target_dir/kvm
if test "$target" = "arm-linux-user" -o "$target" = "armeb-linux-user" -o "$target" = "arm-bsd-user" -o "$target" = "armeb-bsd-user" ; then
mkdir -p $target_dir/nwfpe
fi
+if test "$target" = "unicore32-softmmu" ; then
+ mkdir -p $target_dir/pkunity
+fi
symlink "$source_path/Makefile.target" "$target_dir/Makefile"
diff --git a/default-configs/unicore32-softmmu.mak b/default-configs/unicore32-softmmu.mak
new file mode 100644
index 0000000..7508f75
--- /dev/null
+++ b/default-configs/unicore32-softmmu.mak
@@ -0,0 +1,4 @@
+# Default configuration for unicore32-softmmu
+
+CONFIG_PTIMER=y
+CONFIG_PCKBD=y
--
1.7.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH 8/9] unicore32-softmmu: add config and makefile support
2012-05-25 11:29 ` [Qemu-devel] [PATCH 8/9] unicore32-softmmu: add config and makefile support Guan Xuetao
@ 2012-05-25 11:48 ` Andreas Färber
2012-05-28 10:08 ` guanxuetao
0 siblings, 1 reply; 23+ messages in thread
From: Andreas Färber @ 2012-05-25 11:48 UTC (permalink / raw)
To: Guan Xuetao; +Cc: blauwirbel, qemu-devel
Am 25.05.2012 13:29, schrieb Guan Xuetao:
> This patch adds configure and makefile support for unicore32-softmmu.
> All puv3-soc devices are put into hw/pkunity directory, so this dir
> will be added when unicore32-softmmu is selected.
>
> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
> ---
> Makefile.target | 5 +++++
> arch_init.c | 2 ++
> arch_init.h | 1 +
> configure | 4 ++++
> default-configs/unicore32-softmmu.mak | 4 ++++
> 5 files changed, 16 insertions(+), 0 deletions(-)
> create mode 100644 default-configs/unicore32-softmmu.mak
>
> diff --git a/Makefile.target b/Makefile.target
> index 1582904..2f850d3 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -387,6 +387,11 @@ obj-xtensa-y += core-dc232b.o
> obj-xtensa-y += core-dc233c.o
> obj-xtensa-y += core-fsf.o
>
> +obj-unicore32-y += uc32_softmmu.o
> +obj-unicore32-y += pkunity/puv3.o
> +obj-unicore32-y += pkunity/puv3_intc.o pkunity/puv3_ost.o pkunity/puv3_gpio.o
> +obj-unicore32-y += pkunity/puv3_pm.o pkunity/puv3_dma.o
[snip]
You need to put the Makefile/configure changes into the patches that
introduce the files please, otherwise they cannot be checked for
compiler warnings/errors.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 8/9] unicore32-softmmu: add config and makefile support
2012-05-25 11:48 ` Andreas Färber
@ 2012-05-28 10:08 ` guanxuetao
2012-05-28 13:46 ` Andreas Färber
0 siblings, 1 reply; 23+ messages in thread
From: guanxuetao @ 2012-05-28 10:08 UTC (permalink / raw)
To: Andreas F�rber; +Cc: blauwirbel, Guan Xuetao, qemu-devel
> Am 25.05.2012 13:29, schrieb Guan Xuetao:
>> This patch adds configure and makefile support for unicore32-softmmu.
>> All puv3-soc devices are put into hw/pkunity directory, so this dir
>> will be added when unicore32-softmmu is selected.
>>
>> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
>> ---
>> Makefile.target | 5 +++++
>> arch_init.c | 2 ++
>> arch_init.h | 1 +
>> configure | 4 ++++
>> default-configs/unicore32-softmmu.mak | 4 ++++
>> 5 files changed, 16 insertions(+), 0 deletions(-)
>> create mode 100644 default-configs/unicore32-softmmu.mak
>>
>> diff --git a/Makefile.target b/Makefile.target
>> index 1582904..2f850d3 100644
>> --- a/Makefile.target
>> +++ b/Makefile.target
>> @@ -387,6 +387,11 @@ obj-xtensa-y += core-dc232b.o
>> obj-xtensa-y += core-dc233c.o
>> obj-xtensa-y += core-fsf.o
>>
>> +obj-unicore32-y += uc32_softmmu.o
>> +obj-unicore32-y += pkunity/puv3.o
>> +obj-unicore32-y += pkunity/puv3_intc.o pkunity/puv3_ost.o
>> pkunity/puv3_gpio.o
>> +obj-unicore32-y += pkunity/puv3_pm.o pkunity/puv3_dma.o
> [snip]
>
> You need to put the Makefile/configure changes into the patches that
> introduce the files please, otherwise they cannot be checked for
> compiler warnings/errors.
>
> Andreas
I think the patch series is considered as a whole, and only
compiling/building one device sim-code doesn't make sense. In fact, when
unicore32-softmmu not enabled, the device sim-code isn't going to be
compiled at all.
Guan Xuetao
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [Qemu-devel] [PATCH 8/9] unicore32-softmmu: add config and makefile support
2012-05-28 10:08 ` guanxuetao
@ 2012-05-28 13:46 ` Andreas Färber
0 siblings, 0 replies; 23+ messages in thread
From: Andreas Färber @ 2012-05-28 13:46 UTC (permalink / raw)
To: guanxuetao; +Cc: blauwirbel, Guan Xuetao, qemu-devel
Am 28.05.2012 12:08, schrieb guanxuetao@mprc.pku.edu.cn:
>> Am 25.05.2012 13:29, schrieb Guan Xuetao:
>>> This patch adds configure and makefile support for unicore32-softmmu.
>>> All puv3-soc devices are put into hw/pkunity directory, so this dir
>>> will be added when unicore32-softmmu is selected.
>>>
>>> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
>>> ---
>>> Makefile.target | 5 +++++
>>> arch_init.c | 2 ++
>>> arch_init.h | 1 +
>>> configure | 4 ++++
>>> default-configs/unicore32-softmmu.mak | 4 ++++
>>> 5 files changed, 16 insertions(+), 0 deletions(-)
>>> create mode 100644 default-configs/unicore32-softmmu.mak
>>>
>>> diff --git a/Makefile.target b/Makefile.target
>>> index 1582904..2f850d3 100644
>>> --- a/Makefile.target
>>> +++ b/Makefile.target
>>> @@ -387,6 +387,11 @@ obj-xtensa-y += core-dc232b.o
>>> obj-xtensa-y += core-dc233c.o
>>> obj-xtensa-y += core-fsf.o
>>>
>>> +obj-unicore32-y += uc32_softmmu.o
>>> +obj-unicore32-y += pkunity/puv3.o
>>> +obj-unicore32-y += pkunity/puv3_intc.o pkunity/puv3_ost.o
>>> pkunity/puv3_gpio.o
>>> +obj-unicore32-y += pkunity/puv3_pm.o pkunity/puv3_dma.o
>> [snip]
>>
>> You need to put the Makefile/configure changes into the patches that
>> introduce the files please, otherwise they cannot be checked for
>> compiler warnings/errors.
>>
> I think the patch series is considered as a whole, and only
> compiling/building one device sim-code doesn't make sense. In fact, when
> unicore32-softmmu not enabled, the device sim-code isn't going to be
> compiled at all.
Well, we expect each patch in a series to build warning-free for
bisectability (even if applied in one PULL), and only compiling things
in the final patch does not help. The series should be ordered so that
we can either manually enable it with --target-list=unicore32-softmmu
until it finally gets enabled by default, or like the openrisc target
enables itself by default with some stubs and refines itself over the
next patches.
The other aspect is to make it easy for humans to review your patches
before they can get applied, and personally I find it easier to review
small patches. But opinions are divided on that. The criteria for
acceptance is not just whether your kernel works in the end [*], my
concern is more about how its design aligns with upstream trends like
QOM awareness.
Another thing: It is advisable to place SoC devices (as opposed to the
machine) into Makefile.objs (hw-unicore32-y) so that they get compiled
into libhw32 rather than into the target's directory. That avoids
duplicates when a second endianness or a 64-bit version is introduced.
(Yes, some existing targets violate that principle. I am working towards
fixing it.)
Andreas
[*] It would be helpful if you could share linux-user and softmmu
binaries on the Wiki for us to avoid regressions.
http://wiki.qemu.org/Testing
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH 9/9] unicore32-softmmu: add maintainer information
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
` (7 preceding siblings ...)
2012-05-25 11:29 ` [Qemu-devel] [PATCH 8/9] unicore32-softmmu: add config and makefile support Guan Xuetao
@ 2012-05-25 11:29 ` Guan Xuetao
2012-05-25 11:30 ` [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
2012-05-25 12:09 ` Andreas Färber
10 siblings, 0 replies; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:29 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel, Guan Xuetao
Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
---
MAINTAINERS | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index b45f075..5b6b031 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -394,6 +394,13 @@ M: Alexander Graf <agraf@suse.de>
S: Maintained
F: hw/s390-*.c
+UniCore32 Machines
+-------------
+PKUnity-3 SoC initramfs-with-busybox
+M: Guan Xuetao <gxt@mprc.pku.edu.cn>
+S: Maintained
+F: hw/pkunity/
+
X86 Machines
------------
PC
--
1.7.0.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE ***
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
` (8 preceding siblings ...)
2012-05-25 11:29 ` [Qemu-devel] [PATCH 9/9] unicore32-softmmu: add maintainer information Guan Xuetao
@ 2012-05-25 11:30 ` Guan Xuetao
2012-05-25 12:09 ` Andreas Färber
10 siblings, 0 replies; 23+ messages in thread
From: Guan Xuetao @ 2012-05-25 11:30 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel
On Fri, 2012-05-25 at 19:28 +0800, Guan Xuetao wrote:
> These patches implement softmmu support on unicore32 architecture.
I'm really sorry for the subject.
The subject is: softmmu implementation on UniCore32 ISA
Thanks.
Guan Xuetao
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE ***
2012-05-25 11:28 [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
` (9 preceding siblings ...)
2012-05-25 11:30 ` [Qemu-devel] [PATCH 0/9] *** SUBJECT HERE *** Guan Xuetao
@ 2012-05-25 12:09 ` Andreas Färber
10 siblings, 0 replies; 23+ messages in thread
From: Andreas Färber @ 2012-05-25 12:09 UTC (permalink / raw)
To: Guan Xuetao; +Cc: blauwirbel, qemu-devel
Hello Xuetao,
Am 25.05.2012 13:28, schrieb Guan Xuetao:
> target-unicore32/op_helper.c | 187 +++++++++++++++++++++++-
Your patches add new code to op_helper.c, whereas for other
architectures there's work going on to drop old-style op_helper.c
(examples committed are sparc and alpha; ppc and x86 are on the list).
Maybe you want to consider that at least for the new helpers you're
introducing?
In master I noticed that reset was not implemented for unicore32.
Haven't seen whether that is being implemented somewhere in this series?
You don't indicate what this series is based on so I assume master and
would ask you to rebase onto qom-next branch, which is going to be the
basis for 1.2 (in particular no cpu_state_reset() any more).
Please update cpu_uc32_init() to return UniCore32CPU so that you can use
it in puv3_init() in place of cpu_init(). See cpu_arm_init()/cpu_init()
on master or many more examples on qom-next.
Your static helpers should also prefer to pass around UniCore32CPU *cpu
rather than CPUUniCore32State *env, as my recent patch series starts
moving code out of env and into the CPUState base class.
Some general notes:
* machine_init() declares a function, so does not need a semicolon.
* TypeInfo when immutable (the regular case) should be static const.
* Struct type names should be CamelCase, not _t.
Any chance to split up patch 7 further for review?
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 23+ messages in thread