From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40600) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sd4ZC-0006OX-Jb for qemu-devel@nongnu.org; Fri, 08 Jun 2012 15:09:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sd4ZB-0004C5-0F for qemu-devel@nongnu.org; Fri, 08 Jun 2012 15:09:50 -0400 Received: from am1ehsobe003.messaging.microsoft.com ([213.199.154.206]:1487 helo=am1outboundpool.messaging.microsoft.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sd4ZA-0004Bc-Mc for qemu-devel@nongnu.org; Fri, 08 Jun 2012 15:09:48 -0400 Message-ID: <4FD24DAE.6040709@freescale.com> Date: Fri, 8 Jun 2012 14:08:30 -0500 From: Scott Wood MIME-Version: 1.0 References: <6A3DF150A5B70D4F9B66A25E3F7C888D03D71BC1@039-SN2MPN1-022.039d.mgd.msft.net> <1339153301.24838.49.camel@pasglop> In-Reply-To: <1339153301.24838.49.camel@pasglop> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC] Proposal: PCI/PCIe: inbound BAR0 emulation for PCI controller (Root Complex) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: Wood Scott-B07421 , Yoder Stuart-B08248 , "qemu-devel@nongnu.org" , Bhushan Bharat-R65777 On 06/08/2012 06:01 AM, Benjamin Herrenschmidt wrote: > From there, AFAIK, the MSI code will simply do stl_le_phys, which I > -believe- will hit a BAR that does MMIO decoding for those addresses, > but I'll let people knowing qemu more in depth reply whether that's true > or not. We may run into trouble once we have an in-kernel MPIC (as we do in our internal tree), as QEMU won't be the right destination for the MSI. This is also a problem for the QEMU command line inspecting such MMIO addresses. I guess the answer is to make QEMU properly aware of kernel-emulated MMIO regions. >> 1. Whenever PCI device does need DMA then these windows (inbound and >> outbound ATMUs registers) need to used to translate pci address to >> system physical address (Sometime we also call this as cpu address >> space). This will probably be done by : [Qemu-devel] [PATCH 00/12] >> IOMMU Infrastructure : patch-set ( I am trying to understand these >> patches :-)) > > Yes, that's basically it. The patches allow you to add a set of routines > that will be used for translating DMA accesses to system memory along > with map/unmap operations etc... How easy is it to have multi-level translation -- PCI controller translates PCI transactions to host DMA addresses, and the system IOMMU translates that into a physical address? -Scott