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Date: Mon, 11 Jun 2012 10:03:56 -0500
From: Anthony Liguori <anthony@codemonkey.ws>
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Subject: Re: [Qemu-devel] [RFC] QOMification of AXI stream
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Anthony Liguori <aliguori@us.ibm.com>, Michal Simek <monstr@monstr.eu>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Peter Crosthwaite <peter.crosthwaite@petalogix.com>, Paul Brook <paul@codesourcery.com>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= <afaerber@suse.de>, John Williams <john.williams@petalogix.com>

On 06/11/2012 09:53 AM, Peter Maydell wrote:
> On 11 June 2012 15:38, Edgar E. Iglesias<edgar.iglesias@gmail.com>  wrote:
>> On Mon, Jun 11, 2012 at 02:39:56PM +0100, Peter Maydell wrote:
>>> Ideally the interface used by DMA controllers should be identical to
>>> the interface used by CPUs to talk to the rest of the system: it's
>>> exactly the same bus interface in hardware, after all.
>>
>> I thought we were talking about the interface between the DMA ctrl
>> and the I/O (devices). Not between the DMA and the "memory" bus system.
>
> In hardware (at least for AXI) they're the same thing. A DMA
> controller is a bus master, just like a CPU. They don't care
> whether the slave is RAM or a device, they're just issuing
> memory transactions to addresses.

It looks like the AXI stream interface also includes a word array.  I can't tell 
though whether this is just a decomposed scatter/gather list though.

There doesn't appear to be a notion of an address though.  You could make all 
operations go to address 0 though but it makes me wonder if that's stretching 
the concept of DMA a bit too much.

Regards,

Anthony Liguori

>
> -- PMM