From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:32862) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sgdfb-0001ii-OS for qemu-devel@nongnu.org; Mon, 18 Jun 2012 11:15:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SgdfW-0005s8-Gb for qemu-devel@nongnu.org; Mon, 18 Jun 2012 11:15:11 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:65535) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgdfW-0005pG-AT for qemu-devel@nongnu.org; Mon, 18 Jun 2012 11:15:06 -0400 Received: by pbbro12 with SMTP id ro12so8880877pbb.4 for ; Mon, 18 Jun 2012 08:15:04 -0700 (PDT) Message-ID: <4FDF45F5.1040905@codemonkey.ws> Date: Mon, 18 Jun 2012 10:15:01 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <20120614195458.GB8244@redhat.com> <4FDA4683.6050809@codemonkey.ws> <4FDB77C9.6020901@codemonkey.ws> <20120617082501.GA28089@redhat.com> <4FDF3838.6050608@codemonkey.ws> <20120618143502.GB26540@redhat.com> In-Reply-To: <20120618143502.GB26540@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] q35 chipset support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: jan.kiszka@siemens.com, Jason Baron , qemu-devel@nongnu.org, Markus Armbruster , yamahata@valinux.co.jp, alex.williamson@redhat.com On 06/18/2012 09:35 AM, Michael S. Tsirkin wrote: > On Mon, Jun 18, 2012 at 09:16:24AM -0500, Anthony Liguori wrote: >> On 06/17/2012 03:25 AM, Michael S. Tsirkin wrote: >>> On Fri, Jun 15, 2012 at 12:58:33PM -0500, Anthony Liguori wrote: >>>> The Q35 is much more sophisticated. The PCI-e complex itself can >>>> present interesting topologies and the legacy PCI bus sits within >>>> the PCI-e complex. >>> >>> Ah, so we can mix in PCI as well? Cool. How does >>> such a mixed topology look? >> >> It does, but I'm having a really hard time deciphering the spec >> here. Here's what it says: >> >> "The ICH9 PCI interface provides a 33 MHz, Revision 2.3 implementation. The ICH9 >> integrates a PCI arbiter that supports up to four external PCI bus >> masters in addition to the internal ICH9 requests. This allows for >> combinations of up to four PCI down devices and PCI slots." >> >> So my interpretation of this is that it provides the ability to >> expose legacy PCI slots. I can't get a reading though on how this >> shows up in the PCI topology though. >> >> It sounds like it would show up as a separate PCI domain. >> >> Regards, >> >> Anthony Liguori > > Actually I found a box with ICH9 > http://fpaste.org/VREA/ > or see attached. > > It looks like there's at least one PCI bridge attached to > the host bridge. Right, and it appears to be a 2.3 bridge (the express capability isn't set). I guess that's the mobile PCI expansion slots as it has a flash card reader in it. Regards, Anthony Liguori > >>>