From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:36435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShUK7-00019Q-Od for qemu-devel@nongnu.org; Wed, 20 Jun 2012 19:28:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ShUK6-0005k0-4S for qemu-devel@nongnu.org; Wed, 20 Jun 2012 19:28:31 -0400 Message-ID: <4FE25C92.4080504@freescale.com> Date: Wed, 20 Jun 2012 18:28:18 -0500 From: Scott Wood MIME-Version: 1.0 References: <1340223111-13449-1-git-send-email-agraf@suse.de> <1340223111-13449-9-git-send-email-agraf@suse.de> <4FE24E18.5050106@freescale.com> <4B0DDA93-C8A1-4517-9900-C984998A3591@suse.de> <4FE257B2.4040709@freescale.com> <7377A535-D293-4117-ADC9-275EE23CCAF7@suse.de> In-Reply-To: <7377A535-D293-4117-ADC9-275EE23CCAF7@suse.de> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 8/8] PPC: Add e5500 CPU target List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Caraman Mihai Claudiu-B02008 , qemu-ppc Mailing List , qemu-devel qemu-devel On 06/20/2012 06:10 PM, Alexander Graf wrote: > > On 21.06.2012, at 01:07, Scott Wood wrote: > >> On 06/20/2012 05:59 PM, Alexander Graf wrote: >>> >>> On 21.06.2012, at 00:26, Scott Wood wrote: >>> >>>> On 06/20/2012 03:11 PM, Alexander Graf wrote: >>>>> + /* XXX better abstract into Emb.xxx features */ >>>>> + if (version == fsl_e5500) { >>>>> + spr_register(env, SPR_BOOKE_EPCR, "EPCR", >>>>> + SPR_NOACCESS, SPR_NOACCESS, >>>>> + &spr_read_generic, &spr_write_generic, >>>>> + 0x00000000); >>>>> + spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", >>>>> + SPR_NOACCESS, SPR_NOACCESS, >>>>> + &spr_read_mas73, &spr_write_mas73, >>>>> + 0x00000000); >>>>> + env->reset_msr = (1ULL < MSR_CM); >>>> >>>> That's a funny way of writing "env->reset_msr = 0". :-) >>>> >>>> Assuming you really meant "env->reset_msr = 1ULL << MSR_CM", why? We >>>> enter the kernel in 32-bit mode. It resets in 32-bit mode as well, if >>>> we ever implement that for e5500 QEMU. >>> >>> Hrm. At least my self-compiled kernel did issue an "ld" instruction before going into MSR_CM mode, hence I figured we need it. >> >> You don't need MSR_CM to run 64-bit instructions. It just affects >> masking in certain places. > > Wait - you don't? Is there a comprehensive description on what MSR_CM really does and does not? Not that I know of -- you need to search the ISA for places that mention MSR[CM] or 64-bit mode. -Scott