From: Scott Wood <scottwood@freescale.com>
To: Alexander Graf <agraf@suse.de>
Cc: Caraman Mihai Claudiu-B02008 <B02008@freescale.com>,
qemu-ppc Mailing List <qemu-ppc@nongnu.org>,
qemu-devel qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v2 10/11] PPC: BookE: Support 32 and 64 bit wide MAS2
Date: Thu, 21 Jun 2012 11:04:03 -0500 [thread overview]
Message-ID: <4FE345F3.1010807@freescale.com> (raw)
In-Reply-To: <1340285640-28669-11-git-send-email-agraf@suse.de>
On 06/21/2012 08:33 AM, Alexander Graf wrote:
> The MAS registers on BookE are all 32 bit wide, except for MAS2, which
> can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR
> setting code, so that the guest can never write invalid values in them.
>
> Signed-off-by: Alexander Graf <agraf@suse.de>
> ---
> target-ppc/translate_init.c | 19 ++++++++++++++++++-
> 1 files changed, 18 insertions(+), 1 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 8ff47ae..e6580ff 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -86,6 +86,19 @@ static void spr_write_generic (void *opaque, int sprn, int gprn)
> }
>
> #if !defined(CONFIG_USER_ONLY)
> +static void spr_write_generic32(void *opaque, int sprn, int gprn)
> +{
> +#ifdef TARGET_PPC64
> + TCGv t0 = tcg_temp_new();
> + tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
> + gen_store_spr(sprn, t0);
> + tcg_temp_free(t0);
> + spr_store_dump_spr(sprn);
> +#else
> + spr_write_generic(opaque, sprn, gprn);
> +#endif
> +}
> +
> static void spr_write_clear (void *opaque, int sprn, int gprn)
> {
> TCGv t0 = tcg_temp_new();
> @@ -1597,10 +1610,14 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
> /* TLB assist registers */
> /* XXX : not implemented */
> for (i = 0; i < 8; i++) {
> + void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
> + if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
> + uea_write = &spr_write_generic;
> + }
> if (mas_mask & (1 << i)) {
> spr_register(env, mas_sprn[i], mas_names[i],
> SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> + &spr_read_generic, uea_write,
> 0x00000000);
> }
What does "uea" mean?
-Scott
next prev parent reply other threads:[~2012-06-21 16:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-21 13:33 [Qemu-devel] [PATCH v2 00/11] PPC: e5500 emulation Alexander Graf
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 01/11] dt: make setprop argument static Alexander Graf
2012-06-23 0:47 ` Peter Crosthwaite
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 02/11] PPC: e500: allow users to set the /compatible property via -machine Alexander Graf
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 03/11] uImage: increase the gzip load size Alexander Graf
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 04/11] PPC: Add some booke SPR defines Alexander Graf
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 05/11] PPC: Add support for MSR_CM Alexander Graf
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 06/11] PPC: BookE: Implement EPR SPR Alexander Graf
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 07/11] PPC: BookE: Make ivpr selectable by CPU type Alexander Graf
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 08/11] PPC: Add e5500 CPU target Alexander Graf
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 09/11] PPC: Extract SPR dump generation into its own function Alexander Graf
2012-06-21 13:33 ` [Qemu-devel] [PATCH v2 10/11] PPC: BookE: Support 32 and 64 bit wide MAS2 Alexander Graf
2012-06-21 16:04 ` Scott Wood [this message]
2012-06-21 16:32 ` Alexander Graf
2012-06-21 13:34 ` [Qemu-devel] [PATCH v2 11/11] PPC: BookE206: Bump MAS2 to 64bit Alexander Graf
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