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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7e2adc5bf17sm19114411b3a.38.2025.12.10.06.02.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Dec 2025 06:02:24 -0800 (PST) Message-ID: <4a1d4bb2-2ee7-4405-a192-53af38e5e3fd@redhat.com> Date: Wed, 10 Dec 2025 15:02:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 11/23] intel_iommu_accel: Stick to system MR for IOMMUFD backed host device when x-flts=on Content-Language: en-US To: Zhenzhong Duan , qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com References: <20251117093729.1121324-1-zhenzhong.duan@intel.com> <20251117093729.1121324-12-zhenzhong.duan@intel.com> From: Eric Auger In-Reply-To: <20251117093729.1121324-12-zhenzhong.duan@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/17/25 10:37 AM, Zhenzhong Duan wrote: > When guest enables scalable mode and setup first stage page table, we don't > want to use IOMMU MR but rather continue using the system MR for IOMMUFD > backed host device. > > Then default HWPT in VFIO contains GPA->HPA mappings which could be reused > as nesting parent HWPT to construct nested HWPT in vIOMMU. > > Move vtd_as_key into intel_iommu_internal.h as it's also used by accel code. > > Suggested-by: Yi Liu > Signed-off-by: Zhenzhong Duan same here Reviewed-by: Eric Auger Eric > --- > hw/i386/intel_iommu_accel.h | 6 ++++++ > hw/i386/intel_iommu_internal.h | 11 +++++++++++ > hw/i386/intel_iommu.c | 28 +++++++++++++++------------- > hw/i386/intel_iommu_accel.c | 18 ++++++++++++++++++ > 4 files changed, 50 insertions(+), 13 deletions(-) > > diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h > index 7ebf137a1a..dbe6ee6982 100644 > --- a/hw/i386/intel_iommu_accel.h > +++ b/hw/i386/intel_iommu_accel.h > @@ -15,6 +15,7 @@ > #ifdef CONFIG_VTD_ACCEL > bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, > Error **errp); > +VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); > #else > static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, > VTDHostIOMMUDevice *vtd_hiod, > @@ -24,5 +25,10 @@ static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, > "host IOMMU is incompatible with guest first stage translation"); > return false; > } > + > +static inline VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as) > +{ > + return NULL; > +} > #endif > #endif > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index 02522f64e0..d8dad18304 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -685,4 +685,15 @@ typedef struct VTDHostIOMMUDevice { > uint8_t devfn; > HostIOMMUDevice *hiod; > } VTDHostIOMMUDevice; > + > +/* > + * PCI bus number (or SID) is not reliable since the device is usaully > + * initialized before guest can configure the PCI bridge > + * (SECONDARY_BUS_NUMBER). > + */ > +struct vtd_as_key { > + PCIBus *bus; > + uint8_t devfn; > + uint32_t pasid; > +}; > #endif > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 4ebf56a74f..29e0281af8 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -56,17 +56,6 @@ > #define VTD_PE_GET_SS_LEVEL(pe) \ > (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) > > -/* > - * PCI bus number (or SID) is not reliable since the device is usaully > - * initialized before guest can configure the PCI bridge > - * (SECONDARY_BUS_NUMBER). > - */ > -struct vtd_as_key { > - PCIBus *bus; > - uint8_t devfn; > - uint32_t pasid; > -}; > - > /* bus/devfn is PCI device's real BDF not the aliased one */ > struct vtd_hiod_key { > PCIBus *bus; > @@ -1731,12 +1720,25 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as) > /* Return whether the device is using IOMMU translation. */ > static bool vtd_switch_address_space(VTDAddressSpace *as) > { > + IntelIOMMUState *s; > bool use_iommu, pt; > > assert(as); > > - use_iommu = as->iommu_state->dmar_enabled && !vtd_as_pt_enabled(as); > - pt = as->iommu_state->dmar_enabled && vtd_as_pt_enabled(as); > + s = as->iommu_state; > + use_iommu = s->dmar_enabled && !vtd_as_pt_enabled(as); > + pt = s->dmar_enabled && vtd_as_pt_enabled(as); > + > + /* > + * When guest enables scalable mode and sets up first stage page table, > + * we stick to system MR for IOMMUFD backed host device. Then its > + * default hwpt contains GPA->HPA mappings which is used directly if > + * PGTT=PT and used as nesting parent if PGTT=FST. Otherwise fall back > + * to original processing. > + */ > + if (s->root_scalable && s->fsts && vtd_find_hiod_iommufd(as)) { > + use_iommu = false; > + } > > trace_vtd_switch_address_space(pci_bus_num(as->bus), > VTD_PCI_SLOT(as->devfn), > diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c > index ead6c42879..ebfc503d64 100644 > --- a/hw/i386/intel_iommu_accel.c > +++ b/hw/i386/intel_iommu_accel.c > @@ -50,3 +50,21 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, > "host IOMMU is incompatible with guest first stage translation"); > return false; > } > + > +VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as) > +{ > + IntelIOMMUState *s = as->iommu_state; > + struct vtd_as_key key = { > + .bus = as->bus, > + .devfn = as->devfn, > + }; > + VTDHostIOMMUDevice *vtd_hiod = g_hash_table_lookup(s->vtd_host_iommu_dev, > + &key); > + > + if (vtd_hiod && vtd_hiod->hiod && > + object_dynamic_cast(OBJECT(vtd_hiod->hiod), > + TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { > + return vtd_hiod; > + } > + return NULL; > +}