From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: qemu-stable@nongnu.org
Subject: Re: [PATCH for-8.2] target/arm: Disable SME if SVE is disabled
Date: Tue, 28 Nov 2023 12:02:07 -0600 [thread overview]
Message-ID: <4a6ed3cf-e714-44c2-b438-44e59b469e7a@linaro.org> (raw)
In-Reply-To: <20231127173318.674758-1-peter.maydell@linaro.org>
On 11/27/23 11:33, Peter Maydell wrote:
> There is no architectural requirement that SME implies SVE, but
> our implementation currently assumes it. (FEAT_SME_FA64 does
> imply SVE.) So if you try to run a CPU with eg "-cpu max,sve=off"
> you quickly run into an assert when the guest tries to write to
> SMCR_EL1:
>
> #6 0x00007ffff4b38e96 in __GI___assert_fail
> (assertion=0x5555566e69cb "sm", file=0x5555566e5b24 "../../target/arm/helper.c", line=6865, function=0x5555566e82f0 <__PRETTY_FUNCTION__.31> "sve_vqm1_for_el_sm") at ./assert/assert.c:101
> #7 0x0000555555ee33aa in sve_vqm1_for_el_sm (env=0x555557d291f0, el=2, sm=false) at ../../target/arm/helper.c:6865
> #8 0x0000555555ee3407 in sve_vqm1_for_el (env=0x555557d291f0, el=2) at ../../target/arm/helper.c:6871
> #9 0x0000555555ee3724 in smcr_write (env=0x555557d291f0, ri=0x555557da23b0, value=2147483663) at ../../target/arm/helper.c:6995
> #10 0x0000555555fd1dba in helper_set_cp_reg64 (env=0x555557d291f0, rip=0x555557da23b0, value=2147483663) at ../../target/arm/tcg/op_helper.c:839
> #11 0x00007fff60056781 in code_gen_buffer ()
>
> Avoid this unsupported and slightly odd combination by
> disabling SME when SVE is not present.
>
> Cc: qemu-stable@nongnu.org
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2005
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> '-cpu sve=off,sme=on,sme_fa64=off' crashes in the same way, so just
> turning off FA64 isn't sufficient. Maybe we should support
> SME-no-SVE, but for 8.2 at least turning off SME is better than
> letting users hit an assertion.
My first reaction was simply to change smcr_write, so that it does not compute SVL unless
SM (as otherwise the write does not (immediately) change vector length).
However, as I searched for other uses of sve_vqm1_for_el, I immediately ran into other
places in which are gated solely by isar_feature_aa64_sve. So I think this simple patch
is best for 8.2.
I also slightly wonder if SME && !SVE is a useful combination. AFAIK, while v9 does not
*require* SVE, SVE2 is intended as a replacement for AdvSIMD, and I believe that so far
all v9 cpus have at least 128-bit SVE.
In any case, I'll work on any improvements in this area for next cycle.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
prev parent reply other threads:[~2023-11-28 18:03 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-27 17:33 [PATCH for-8.2] target/arm: Disable SME if SVE is disabled Peter Maydell
2023-11-28 15:39 ` Cornelia Huck
2023-11-28 18:02 ` Richard Henderson [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4a6ed3cf-e714-44c2-b438-44e59b469e7a@linaro.org \
--to=richard.henderson@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-stable@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).