Re: [PATCH for-10.1 4/6] target/arm: LD1Q, ST1Q are vector + scalar, not scalar + vector

[Richard Henderson <richard.henderson@linaro.org>]

On 7/23/25 09:54, Peter Maydell wrote:
> Unlike the "LD1D (scalar + vector)" etc instructions, LD1Q is
> vector + scalar. This means that:
>   * the vector and the scalar register are in opposite fields
>     in the encoding
>   * 31 in the scalar register field is XZR, not XSP
> 
> The same applies for ST1Q.
> 
> This means we can't reuse the trans_LD1_zprz() and trans_ST1_zprz()
> functions for LD1Q and ST1Q. Split them out to use their own
> trans functions.
> 
> Note that the change made here to sve.decode requires the decodetree
> bugfix "decodetree: Infer argument set before inferring format" to
> avoid a spurious compile-time error about "dtype".
> 
> Fixes: d2aa9a804ee678f ("target/arm: Implement LD1Q, ST1Q for SVE2p1")
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/arm/tcg/sve.decode      | 12 +++----
>   target/arm/tcg/translate-sve.c | 65 ++++++++++++++++++++++++++--------
>   2 files changed, 57 insertions(+), 20 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~