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Sat, 22 Nov 2025 02:22:25 -0500 Received: from mxplan5.mail.ovh.net (unknown [10.109.254.9]) by mo529.mail-out.ovh.net (Postfix) with ESMTPS id 4dD3Rs1Xlqz5w9L; Sat, 22 Nov 2025 07:21:44 +0000 (UTC) Received: from kaod.org (37.59.142.109) by DAG8EX2.mxp5.local (172.16.2.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.61; Sat, 22 Nov 2025 08:21:43 +0100 Authentication-Results: garm.ovh; auth=pass (GARM-109S00322e31a61-ac32-4874-9c79-5ca650d85bbf, BDE5E08CAA5430CDD034853EEFE7ADF510FDB634) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Message-ID: <4a893b67-c457-47a5-87ca-c41c0a4df070@kaod.org> Date: Sat, 22 Nov 2025 08:21:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [SPAM] [PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug To: Jamin Lin , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , References: <20251121050108.3407445-1-jamin_lin@aspeedtech.com> <20251121050108.3407445-2-jamin_lin@aspeedtech.com> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= Content-Language: en-US, fr Autocrypt: addr=clg@kaod.org; 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charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [37.59.142.109] X-ClientProxiedBy: DAG9EX2.mxp5.local (172.16.2.82) To DAG8EX2.mxp5.local (172.16.2.72) X-Ovh-Tracer-GUID: 0ff04f64-22aa-4a0e-aa86-1bf2c87cfa1e X-Ovh-Tracer-Id: 7244040004386982834 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: dmFkZTGH6v95T7keEROrGFMTV1WVXfmCiamPW936P49pNYF8bJmaR+0VgpmSRxNrnZNqEXCLVE46Du0ctieMjfBfwVoFUoIHsW3CGunMY84ykB5AWMmqi7JPcuRDvOEZVQo9dnBpaPFKZGVKk4D7bSIHjPvyL/AoDggzR2jhqIBH3BSQ8YoaAtLXdaZSVTy3l0V1D10aY3dS/WTyIXhZsJ3BRMw7F8OD7O3sJ78fjwTpuPNOg+xEc+0qdEaYq3ZGqH6w76D+4u3gU7jzEU01JztSEm5uuC6AQ2tqmdoFkhCqOkT0uvSOsvgkHrffG+pWhuTiPOs2D3v9QYmWkEl7fSUktoGSsxTpgONqWzRpTNzYP1YYJmy32zB7dlOVYgcWwOxGESerRHq9UKWcok/+mm6ip8PTo7ohtG4nsR3aP3x9XAzWSDwhJRVaACFZkiZ91Tk/zLMnWjVwhupHrbgJMidHtk9/LRQYEfGy1KMf0CgrvysqHv19QHuYTzaNS+mO8iDEhsSPSfLgcX0P6fJmjSE+8/ufQyPyH2SFMNaKcTZYrrlHoAYszLJuianr4Q1eNgq8z9Mku26V1YqNnA4kajPzC/ZZqGh6QNmhsDxOndLBqOHP3PX1IuuAK29BLtyttILh9WbMKCVMc7eCmtcfZpTLHR8iVTA6nbaPdMFC6Rn7Xfjgow DKIM-Signature: a=rsa-sha256; bh=xZGzjLqXk74K0JYHVocJhDdupdJvlc3jlXUjzNR7uls=; c=relaxed/relaxed; d=kaod.org; h=From; s=ovhmo393970-selector1; t=1763796106; v=1; b=Uz/d9LnTJ7MhmBqKly5E0lb68OE4+wAPQGGPQdefWuIa+RdiB/kw+s5H2VVk8pB0ptYP+Gzy oWlfFdR5IPq9+B649S+RyPmNBYdLDhaZmsSN1g2pESgNskp92UyK0IMtwBbuVOXJnwSvvZtUzmj L4QfG/2TBJoq7zskoCIpsdyjK4SS5soRkLSlPDJfo37J05N4HPErqnJSCU+PoBF+c22zHVM1sCm zyTeeWnttk7gx2/uAQjXk8fRwj1W0QB4BK3QpwklhMhK7Kcgi58+4NClhUiEhIndgIE0Y+H/NZO ymTMLBODbtEkz+hGG/IXb8WmtfVJ2z5ZUtTFnDHBfvX9w== Received-SPF: pass client-ip=178.32.125.2; envelope-from=clg@kaod.org; helo=smtpout1.mo529.mail-out.ovh.net X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/21/25 06:01, Jamin Lin wrote: > This patch updates the ASPEED PCIe Root Port capability layout and interrupt > handling to match the hardware-defined capability structure as documented in > the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet. > > The following capability offsets and fields are now aligned with the actual > hardware implementation (validated using EVB config-space dumps via > 'lspci -s -vvv'): > > - Added MSI capability at offset 0x50 and enabled 1-vector MSI support > - Added PCI Express Capability structure at offset 0x80 > - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0 > - Added AER capability at offset 0x100 > - Implemented aer_vector() callback and MSI init/uninit hooks > - Updated Root Port SSID to 0x1150 to reflect the platform default > > Enabling MSI is required for proper PCIe Hotplug event signaling. This change > improves correctness and ensures QEMU Root Port behavior matches the behavior > of ASPEED hardware and downstream kernel expectations. > > Signed-off-by: Jamin Lin Fixes: 2af56518fa91 ("hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable") Reviewed-by: Cédric Le Goater Thanks, C. > --- > hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++- > 1 file changed, 39 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c > index f7593444fc..1fc2c61772 100644 > --- a/hw/pci-host/aspeed_pcie.c > +++ b/hw/pci-host/aspeed_pcie.c > @@ -68,6 +68,38 @@ static const TypeInfo aspeed_pcie_root_device_info = { > * PCIe Root Port > */ > > +#define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET 0x50 > +#define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR 1 > +#define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET 0xC0 > +#define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET 0x80 > +#define ASPEED_PCIE_ROOT_PORT_AER_OFFSET 0x100 > + > +static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d) > +{ > + return 0; > +} > + > +static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **errp) > +{ > + int rc; > + > + rc = msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET, > + ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR, > + PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT, > + PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT, > + errp); > + if (rc < 0) { > + assert(rc == -ENOTSUP); > + } > + > + return rc; > +} > + > +static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d) > +{ > + msi_uninit(d); > +} > + > static void aspeed_pcie_root_port_class_init(ObjectClass *klass, > const void *data) > { > @@ -80,7 +112,13 @@ static void aspeed_pcie_root_port_class_init(ObjectClass *klass, > k->device_id = 0x1150; > dc->user_creatable = true; > > - rpc->aer_offset = 0x100; > + rpc->aer_vector = aspeed_pcie_root_port_aer_vector; > + rpc->interrupts_init = aspeed_pcie_root_port_interrupts_init; > + rpc->interrupts_uninit = aspeed_pcie_root_port_interrupts_uninit; > + rpc->exp_offset = ASPEED_PCIE_ROOT_PORT_EXP_OFFSET; > + rpc->aer_offset = ASPEED_PCIE_ROOT_PORT_AER_OFFSET; > + rpc->ssvid_offset = ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET; > + rpc->ssid = 0x1150; > } > > static const TypeInfo aspeed_pcie_root_port_info = {