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Wed, 07 Feb 2024 00:56:16 -0800 (PST) Message-ID: <4a99697d-99fb-4df5-a6d2-4ea4e4214437@linaro.org> Date: Wed, 7 Feb 2024 09:56:14 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/13] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20240206132931.38376-1-peter.maydell@linaro.org> <20240206132931.38376-8-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240206132931.38376-8-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/2/24 14:29, Peter Maydell wrote: > The MPS2 SCC device is broadly the same for all FPGA images, but has > minor differences in the behaviour of the CFG registers depending on > the image. In many cases we don't really care about the functionality > controlled by these registers and a reads-as-written or similar > behaviour is sufficient for the moment. > > For the AN536 the required behaviour is: > > * A_CFG0 has CPU reset and halt bits > - implement as reads-as-written for the moment > * A_CFG1 has flash or ATCM address 0 remap handling > - QEMU doesn't model this; implement as reads-as-written > * A_CFG2 has QSPI select (like AN524) > - implemented (no behaviour, as with AN524) > * A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits" > - QEMU doesn't care about these, so use the existing > RAZ behaviour for convenience > * A_CFG4 is board rev (like all other images) > - no change needed > * A_CFG5 is ACLK frq in hz (like AN524) > - implemented as reads-as-written, as for other boards > * A_CFG6 is core 0 vector table base address > - implemented as reads-as-written for the moment > * A_CFG7 is core 1 vector table base address > - implemented as reads-as-written for the moment > > Make the changes necessary for this; leave TODO comments where > appropriate to indicate where we might want to come back and > implement things like CPU reset. > > The other aspects of the device specific to this FPGA image (like the > values of the board ID and similar registers) will be set via the > device's qdev properties. > > Signed-off-by: Peter Maydell > --- > include/hw/misc/mps2-scc.h | 1 + > hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++---- > 2 files changed, 92 insertions(+), 10 deletions(-) Reviewed-by: Philippe Mathieu-Daudé