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[81.185.164.116]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfdfad7sm21029040f8f.26.2025.03.12.07.28.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 07:28:20 -0700 (PDT) Message-ID: <4aa4c71d-fe82-423b-80a5-886a7446025d@linaro.org> Date: Wed, 12 Mar 2025 15:28:19 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] Revert "hw/char/pl011: Warn when using disabled receiver" To: Peter Maydell , Paolo Bonzini Cc: qemu-devel@nongnu.org References: <20250311153717.206129-1-pbonzini@redhat.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/3/25 14:43, Peter Maydell wrote: > On Wed, 12 Mar 2025 at 13:36, Peter Maydell wrote: >> >> On Tue, 11 Mar 2025 at 15:37, Paolo Bonzini wrote: >>> >>> The guest does not control whether characters are sent on the UART. >>> Sending them before the guest happens to boot will now result in a >>> "guest error" log entry that is only because of timing, even if the >>> guest _would_ later setup the receiver correctly. >>> >>> This reverts commit abf2b6a028670bd2890bb3aee7e103fe53e4b0df, apart >>> from adding the comment. >>> >>> Cc: Philippe Mathieu-Daudé >>> Cc: Peter Maydell >>> Signed-off-by: Paolo Bonzini >>> --- >>> hw/char/pl011.c | 12 ++---------- >>> 1 file changed, 2 insertions(+), 10 deletions(-) >>> >>> diff --git a/hw/char/pl011.c b/hw/char/pl011.c >>> index 23a9db8c57c..efca8baecd7 100644 >>> --- a/hw/char/pl011.c >>> +++ b/hw/char/pl011.c >>> @@ -85,7 +85,6 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) >>> #define CR_OUT1 (1 << 12) >>> #define CR_RTS (1 << 11) >>> #define CR_DTR (1 << 10) >>> -#define CR_RXE (1 << 9) >>> #define CR_TXE (1 << 8) >>> #define CR_LBE (1 << 7) >>> #define CR_UARTEN (1 << 0) >>> @@ -490,16 +489,9 @@ static int pl011_can_receive(void *opaque) >>> unsigned fifo_depth = pl011_get_fifo_depth(s); >>> unsigned fifo_available = fifo_depth - s->read_count; >>> >>> - if (!(s->cr & CR_UARTEN)) { >>> - qemu_log_mask(LOG_GUEST_ERROR, >>> - "PL011 receiving data on disabled UART\n"); >>> - } >>> - if (!(s->cr & CR_RXE)) { >>> - qemu_log_mask(LOG_GUEST_ERROR, >>> - "PL011 receiving data on disabled RX UART\n"); >>> - } >>> + /* Should check enable and return 0? */ >> >> We decided deliberately not to check the enable and return 0 >> here, as described in the commit message of abf2b6a028670bd: >> we think there's too likely to be existing works-on-QEMU code >> out there that doesn't ever set the enable bits. >> >> Otherwise, yes, agreed with the revert. > > Oh, and I just realized that the right place to diagnose > "guest didn't enable the UART" would be when it reads/writes > the data register while the enable bits are clear. Doh, sorry. I wonder how I ended putting this code here... Since I rebased this a lot, maybe something went wrong. Anyway, I'll post a fix. Regards, Phil.