Hello All,<div><br></div><div>I have a question about read permissions of TBL SPR for all ppc processors:</div><div>I have discovered that my application, compiled by WindRiver diab compiler and running in vxworks OS on ppc405 architecture bumps into exception generated when trying to read TBL or TBU registers:</div>
<div><br></div><div><br></div><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;"><div><div>program</div></div><div><div>Exception current instruction address: 0x0003eb28</div>
</div><div><div>Machine Status Register: 0x00088200</div></div><div><div>Condition Register: 0x40000440</div></div><div><div><br></div></div><div><div>&lt;&lt;&lt;&lt;&lt;Registers&gt;&gt;&gt;&gt;&gt;</div></div><div><div>
<br></div></div><div><div>.....</div></div><div><div><br></div></div><div><div>&lt;&lt;&lt;&lt;&lt;Disassembly&gt;&gt;&gt;&gt;&gt;</div></div><div><div><br></div></div><div><div> 0x3eb08  4e800020    blr</div></div><div><div>
 0x3eb0c  3860ffff    li          r3,0xffff # -1</div></div><div><div> 0x3eb10  4e800020    blr</div></div><div><div> 0x3eb14  38a00000    li          r5,0x0 # 0</div></div><div><div> 0x3eb18  7cbc43a6    mtspr       TBL,r5</div>
</div><div><div> 0x3eb1c  7c7d43a6    mtspr       TBU,r3</div></div><div><div> 0x3eb20  7c9c43a6    mtspr       TBL,r4</div></div><div><div> 0x3eb24  4e800020    blr</div></div><div><div>*0x3eb28  7cbd42a6    mfspr       r5,TBU</div>
</div><div><div> 0x3eb2c  7cdc42a6    mfspr       r6,TBL</div></div><div><div> 0x3eb30  7cfd42a6     mfspr       r7,TBU</div></div><div><div> 0x3eb34  7c053800    cmp         crf0,0,r5,r7</div></div><div><div> 0x3eb38  4082fff0       bc          0x4,2, 0x3eb28 # vxTimeBaseGet</div>
</div><div><div> 0x3eb3c  90a30000    stw         r5,0(r3)</div></div><div><div> 0x3eb40  90c40000    stw         r6,0(r4)</div></div><div><div> 0x3eb44  4e800020    blr</div></div><div><div><br></div></div><div><div>&lt;&lt;&lt;&lt;&lt;Traceback&gt;&gt;&gt;&gt;&gt;</div>
<div>......</div></div></blockquote><div><br></div><div>I looked into qemu mfspr instruction implementation and discovered that for some reason qemu had set NOACCESS permissions for reading this register upon CPU initialization:</div>
<div><br></div><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;"><div><div>/* Generic PowerPC time base */</div></div><div><div>static void gen_tbl (CPUPPCState *env)</div>
</div><div><div>{</div></div><div><div>    spr_register(env, SPR_VTBL,  &quot;TBL&quot;,</div></div><div><div>                 &amp;spr_read_tbl, SPR_NOACCESS,</div></div><div><div>                 &amp;spr_read_tbl, SPR_NOACCESS,</div>
</div><div><div>                 0x00000000);</div></div><div><div>    spr_register(env, SPR_TBL,   &quot;TBL&quot;,</div></div><div><div>                 <b>SPR_NOACCESS</b>, SPR_NOACCESS,</div></div><div><div>                 <b>SPR_NOACCESS</b>, &amp;spr_write_tbl,</div>
</div><div><div>                 0x00000000);</div></div><div><div>    spr_register(env, SPR_VTBU,  &quot;TBU&quot;,</div></div><div><div>                 &amp;spr_read_tbu, SPR_NOACCESS,</div></div><div><div>                 &amp;spr_read_tbu, SPR_NOACCESS,</div>
</div><div><div>                 0x00000000);</div></div><div><div>    spr_register(env, SPR_TBU,   &quot;TBU&quot;,</div></div><div><div>                 <b>SPR_NOACCESS</b>, SPR_NOACCESS,</div></div><div><div>                 <b>SPR_NOACCESS</b>, &amp;spr_write_tbu,</div>
</div><div><div>                 0x00000000);</div></div><div><div>}</div></div></blockquote><div><br></div><div>Is this a right thing to do? it&#39;s certainly either qemu bug or diab bug (which i don&#39;t think is likely, cause this code has been running on the real hw without any issues)</div>
<div><br></div><div><br></div><div>BR,</div><div>Dmitry I.<br>-- <br><br><br><a href="http://www.brainyquote.com/quotes/authors/j/jonathan_swift.html" target="_blank">Jonathan Swift</a>  - &quot;May you live every day of your life.&quot;
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