* [Qemu-devel] TBL register permissions for PPC
@ 2009-12-01 18:33 Dima Ilyevsky
2009-12-01 19:28 ` Krumme, Chris
2009-12-01 23:23 ` Alexander Graf
0 siblings, 2 replies; 9+ messages in thread
From: Dima Ilyevsky @ 2009-12-01 18:33 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2362 bytes --]
Hello All,
I have a question about read permissions of TBL SPR for all ppc processors:
I have discovered that my application, compiled by WindRiver diab compiler
and running in vxworks OS on ppc405 architecture bumps into exception
generated when trying to read TBL or TBU registers:
program
Exception current instruction address: 0x0003eb28
Machine Status Register: 0x00088200
Condition Register: 0x40000440
<<<<<Registers>>>>>
.....
<<<<<Disassembly>>>>>
0x3eb08 4e800020 blr
0x3eb0c 3860ffff li r3,0xffff # -1
0x3eb10 4e800020 blr
0x3eb14 38a00000 li r5,0x0 # 0
0x3eb18 7cbc43a6 mtspr TBL,r5
0x3eb1c 7c7d43a6 mtspr TBU,r3
0x3eb20 7c9c43a6 mtspr TBL,r4
0x3eb24 4e800020 blr
*0x3eb28 7cbd42a6 mfspr r5,TBU
0x3eb2c 7cdc42a6 mfspr r6,TBL
0x3eb30 7cfd42a6 mfspr r7,TBU
0x3eb34 7c053800 cmp crf0,0,r5,r7
0x3eb38 4082fff0 bc 0x4,2, 0x3eb28 # vxTimeBaseGet
0x3eb3c 90a30000 stw r5,0(r3)
0x3eb40 90c40000 stw r6,0(r4)
0x3eb44 4e800020 blr
<<<<<Traceback>>>>>
......
I looked into qemu mfspr instruction implementation and discovered that for
some reason qemu had set NOACCESS permissions for reading this register upon
CPU initialization:
/* Generic PowerPC time base */
static void gen_tbl (CPUPPCState *env)
{
spr_register(env, SPR_VTBL, "TBL",
&spr_read_tbl, SPR_NOACCESS,
&spr_read_tbl, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBL, "TBL",
*SPR_NOACCESS*, SPR_NOACCESS,
*SPR_NOACCESS*, &spr_write_tbl,
0x00000000);
spr_register(env, SPR_VTBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBU, "TBU",
*SPR_NOACCESS*, SPR_NOACCESS,
*SPR_NOACCESS*, &spr_write_tbu,
0x00000000);
}
Is this a right thing to do? it's certainly either qemu bug or diab bug
(which i don't think is likely, cause this code has been running on the real
hw without any issues)
BR,
Dmitry I.
--
Jonathan Swift<http://www.brainyquote.com/quotes/authors/j/jonathan_swift.html>
- "May you live every day of your life."
[-- Attachment #2: Type: text/html, Size: 4320 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [Qemu-devel] TBL register permissions for PPC
2009-12-01 18:33 [Qemu-devel] TBL register permissions for PPC Dima Ilyevsky
@ 2009-12-01 19:28 ` Krumme, Chris
2009-12-01 23:23 ` Alexander Graf
1 sibling, 0 replies; 9+ messages in thread
From: Krumme, Chris @ 2009-12-01 19:28 UTC (permalink / raw)
To: Dima Ilyevsky, qemu-devel
________________________________
From: qemu-devel-bounces+chris.krumme=windriver.com@nongnu.org
[mailto:qemu-devel-bounces+chris.krumme=windriver.com@nongnu.org] On
Behalf Of Dima Ilyevsky
Sent: Tuesday, December 01, 2009 12:33 PM
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] TBL register permissions for PPC
Hello All,
I have a question about read permissions of TBL SPR for all ppc
processors:
I have discovered that my application, compiled by WindRiver
diab compiler and running in vxworks OS on ppc405 architecture bumps
into exception generated when trying to read TBL or TBU registers:
Hello Dmitry,
The code in question comes from hand coded area's so this is probably
not a compiler issue, now maybe there is an issue with the BSP, but that
is a different question.
Does the 405 manual indicate readability of that register?
Thanks
Chris
program
Exception current instruction address: 0x0003eb28
Machine Status Register: 0x00088200
Condition Register: 0x40000440
<<<<<Registers>>>>>
.....
<<<<<Disassembly>>>>>
0x3eb08 4e800020 blr
0x3eb0c 3860ffff li r3,0xffff # -1
0x3eb10 4e800020 blr
0x3eb14 38a00000 li r5,0x0 # 0
0x3eb18 7cbc43a6 mtspr TBL,r5
0x3eb1c 7c7d43a6 mtspr TBU,r3
0x3eb20 7c9c43a6 mtspr TBL,r4
0x3eb24 4e800020 blr
*0x3eb28 7cbd42a6 mfspr r5,TBU
0x3eb2c 7cdc42a6 mfspr r6,TBL
0x3eb30 7cfd42a6 mfspr r7,TBU
0x3eb34 7c053800 cmp crf0,0,r5,r7
0x3eb38 4082fff0 bc 0x4,2, 0x3eb28 #
vxTimeBaseGet
0x3eb3c 90a30000 stw r5,0(r3)
0x3eb40 90c40000 stw r6,0(r4)
0x3eb44 4e800020 blr
<<<<<Traceback>>>>>
......
I looked into qemu mfspr instruction implementation and
discovered that for some reason qemu had set NOACCESS permissions for
reading this register upon CPU initialization:
/* Generic PowerPC time base */
static void gen_tbl (CPUPPCState *env)
{
spr_register(env, SPR_VTBL, "TBL",
&spr_read_tbl, SPR_NOACCESS,
&spr_read_tbl, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBL, "TBL",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, &spr_write_tbl,
0x00000000);
spr_register(env, SPR_VTBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBU, "TBU",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, &spr_write_tbu,
0x00000000);
}
Is this a right thing to do? it's certainly either qemu bug or
diab bug (which i don't think is likely, cause this code has been
running on the real hw without any issues)
BR,
Dmitry I.
--
Jonathan Swift
<http://www.brainyquote.com/quotes/authors/j/jonathan_swift.html> -
"May you live every day of your life."
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] TBL register permissions for PPC
2009-12-01 18:33 [Qemu-devel] TBL register permissions for PPC Dima Ilyevsky
2009-12-01 19:28 ` Krumme, Chris
@ 2009-12-01 23:23 ` Alexander Graf
2009-12-01 23:35 ` malc
2010-03-24 21:56 ` Dmitry Ilyevsky
1 sibling, 2 replies; 9+ messages in thread
From: Alexander Graf @ 2009-12-01 23:23 UTC (permalink / raw)
To: Dima Ilyevsky; +Cc: qemu-devel
On 01.12.2009, at 19:33, Dima Ilyevsky wrote:
> Hello All,
>
> I have a question about read permissions of TBL SPR for all ppc processors:
> I have discovered that my application, compiled by WindRiver diab compiler and running in vxworks OS on ppc405 architecture bumps into exception generated when trying to read TBL or TBU registers:
Unless Linux does something funky, mftlb, mftbu (and mftb on 64 bit) are readable from PR=1.
int main()
{
long tbu=0, tbl=0;
asm("mftbu %0" : "=r" (tbu));
asm("mftbl %0" : "=r" (tbl));
printf("TB: %#x %#x\n", tbl, tbu);
}
agraf@lychee:/tmp> ./mftb
TB: 0xc0397180 0x603
However it can't be written to:
asm("mttbl %0" : : "r" (tbl));
agraf@lychee:/tmp> ./mftb
Illegal instruction
So yes, I'd suspect a bug in qemu here. Feel free to send a patch.
Alex
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] TBL register permissions for PPC
2009-12-01 23:23 ` Alexander Graf
@ 2009-12-01 23:35 ` malc
2010-03-24 21:56 ` Dmitry Ilyevsky
1 sibling, 0 replies; 9+ messages in thread
From: malc @ 2009-12-01 23:35 UTC (permalink / raw)
To: Alexander Graf; +Cc: Dima Ilyevsky, qemu-devel
On Wed, 2 Dec 2009, Alexander Graf wrote:
>
> On 01.12.2009, at 19:33, Dima Ilyevsky wrote:
>
> > Hello All,
> >
> > I have a question about read permissions of TBL SPR for all ppc processors:
> > I have discovered that my application, compiled by WindRiver diab compiler and running in vxworks OS on ppc405 architecture bumps into exception generated when trying to read TBL or TBU registers:
>
> Unless Linux does something funky, mftlb, mftbu (and mftb on 64 bit) are readable from PR=1.
>
> int main()
> {
> long tbu=0, tbl=0;
>
> asm("mftbu %0" : "=r" (tbu));
> asm("mftbl %0" : "=r" (tbl));
>
> printf("TB: %#x %#x\n", tbl, tbu);
> }
>
> agraf@lychee:/tmp> ./mftb
> TB: 0xc0397180 0x603
>
> However it can't be written to:
>
> asm("mttbl %0" : : "r" (tbl));
>
> agraf@lychee:/tmp> ./mftb
> Illegal instruction
7.2.1 Writing the Time Base
Writing the Time Base is privileged, and can be done
only in hypervisor state. Reading the Time Base is not
privileged; it is discussed in Chapter 4 of Book II.
>
>
> So yes, I'd suspect a bug in qemu here. Feel free to send a patch.
>
> Alex
>
--
mailto:av1474@comtv.ru
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] TBL register permissions for PPC
2009-12-01 23:23 ` Alexander Graf
2009-12-01 23:35 ` malc
@ 2010-03-24 21:56 ` Dmitry Ilyevsky
2010-03-25 7:53 ` Alexander Graf
1 sibling, 1 reply; 9+ messages in thread
From: Dmitry Ilyevsky @ 2010-03-24 21:56 UTC (permalink / raw)
To: Alexander Graf, Krumme, Chris; +Cc: qemu-devel
[-- Attachment #1.1: Type: text/plain, Size: 1350 bytes --]
Hello All,
Please review patch for TBL SPR read access for generic PPC.
*Description:*
POWER specification docs define TBL/TBU SPRs as readable in user
and privileged modes. Therefore SPRs permissions were changed in gen_tbl
function in target-ppc/translate_init.c file.
*Testing:*
Tested with vxworks-6.2 bsp and OS on custom qemu board that includes ppc405
emulated core
BR,
Dmitry Ilyevsky
On Wed, Dec 2, 2009 at 2:23 AM, Alexander Graf <agraf@suse.de> wrote:
>
> On 01.12.2009, at 19:33, Dima Ilyevsky wrote:
>
> > Hello All,
> >
> > I have a question about read permissions of TBL SPR for all ppc
> processors:
> > I have discovered that my application, compiled by WindRiver diab
> compiler and running in vxworks OS on ppc405 architecture bumps into
> exception generated when trying to read TBL or TBU registers:
>
> Unless Linux does something funky, mftlb, mftbu (and mftb on 64 bit) are
> readable from PR=1.
>
> int main()
> {
> long tbu=0, tbl=0;
>
> asm("mftbu %0" : "=r" (tbu));
> asm("mftbl %0" : "=r" (tbl));
>
> printf("TB: %#x %#x\n", tbl, tbu);
> }
>
> agraf@lychee:/tmp> ./mftb
> TB: 0xc0397180 0x603
>
> However it can't be written to:
>
> asm("mttbl %0" : : "r" (tbl));
>
> agraf@lychee:/tmp> ./mftb
> Illegal instruction
>
>
> So yes, I'd suspect a bug in qemu here. Feel free to send a patch.
>
> Alex
>
[-- Attachment #1.2: Type: text/html, Size: 2077 bytes --]
[-- Attachment #2: 0001-Generic-PowerPC-time-base-SPR-should-be-accessible-i.patch --]
[-- Type: text/x-patch, Size: 1365 bytes --]
From 141bf29f5355f163205c57e98590730ed15bfb86 Mon Sep 17 00:00:00 2001
From: n/a <install@ubuntu-desktop.(none)>
Date: Thu, 25 Mar 2010 00:22:25 +0300
Subject: [PATCH] Generic PowerPC time base SPR should be accessible in user/priv modes for reading
---
target-ppc/translate_init.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index db4dc17..e8eadf4 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -777,16 +777,16 @@ static void gen_tbl (CPUPPCState *env)
&spr_read_tbl, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBL, "TBL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbl,
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, &spr_write_tbl,
0x00000000);
spr_register(env, SPR_VTBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBU, "TBU",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbu,
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, &spr_write_tbu,
0x00000000);
}
--
1.7.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] TBL register permissions for PPC
2010-03-24 21:56 ` Dmitry Ilyevsky
@ 2010-03-25 7:53 ` Alexander Graf
2010-03-26 0:31 ` Dmitry Ilyevsky
0 siblings, 1 reply; 9+ messages in thread
From: Alexander Graf @ 2010-03-25 7:53 UTC (permalink / raw)
To: Dmitry Ilyevsky; +Cc: Krumme, Chris, qemu-devel
On 24.03.2010, at 22:56, Dmitry Ilyevsky wrote:
>
> Hello All,
>
> Please review patch for TBL SPR read access for generic PPC.
>
> Description:
>
> POWER specification docs define TBL/TBU SPRs as readable in user and privileged modes. Therefore SPRs permissions were changed in gen_tbl function in target-ppc/translate_init.c file.
>
> Testing:
>
> Tested with vxworks-6.2 bsp and OS on custom qemu board that includes ppc405 emulated core
A couple of comments to this patch.
1) Please don't top-post.
2) Always put a Signed-off-by: in the patch
3) Put the patch description into the patch, so git knows what to do with it
4) Don't use html features in mail :-)
The patch looks good otherwise.
Alex
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] TBL register permissions for PPC
2010-03-25 7:53 ` Alexander Graf
@ 2010-03-26 0:31 ` Dmitry Ilyevsky
2010-03-26 1:15 ` Alexander Graf
2010-03-26 22:42 ` Aurelien Jarno
0 siblings, 2 replies; 9+ messages in thread
From: Dmitry Ilyevsky @ 2010-03-26 0:31 UTC (permalink / raw)
To: Alexander Graf; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 849 bytes --]
On Thu, Mar 25, 2010 at 10:53 AM, Alexander Graf <agraf@suse.de> wrote:
>
> On 24.03.2010, at 22:56, Dmitry Ilyevsky wrote:
>
>>
>> Hello All,
>>
>> Please review patch for TBL SPR read access for generic PPC.
>>
>> Description:
>>
>> POWER specification docs define TBL/TBU SPRs as readable in user and privileged modes. Therefore SPRs permissions were changed in gen_tbl function in target-ppc/translate_init.c file.
>>
>> Testing:
>>
>> Tested with vxworks-6.2 bsp and OS on custom qemu board that includes ppc405 emulated core
>
> A couple of comments to this patch.
>
> 1) Please don't top-post.
> 2) Always put a Signed-off-by: in the patch
> 3) Put the patch description into the patch, so git knows what to do with it
> 4) Don't use html features in mail :-)
>
> The patch looks good otherwise.
>
>
> Alex
>
>
Corrected.
Thanks,
Dmitry I.
[-- Attachment #2: 0001-Generic-PowerPC-TBL.patch --]
[-- Type: text/x-patch, Size: 1526 bytes --]
From b5846b7df136c1eff7df8dada8800c81e1799cf4 Mon Sep 17 00:00:00 2001
From: Dmitry Ilyevsky <ilyevsky@gmail.com>
Date: Fri, 26 Mar 2010 03:25:36 +0300
Subject: Generic PowerPC TBL
Time base SPRs TBL/TBU should be accessible in user/priv modes for reading as specified in POWER ISA documentation. Therefore SPRs permissions were changed in gen_tbl function.
Signed-off-by: Dmitry Ilyevsky <ilyevsky@gmail.com>
---
target-ppc/translate_init.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index db4dc17..e8eadf4 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -777,16 +777,16 @@ static void gen_tbl (CPUPPCState *env)
&spr_read_tbl, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBL, "TBL",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbl,
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, &spr_write_tbl,
0x00000000);
spr_register(env, SPR_VTBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, SPR_NOACCESS,
0x00000000);
spr_register(env, SPR_TBU, "TBU",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_tbu,
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, &spr_write_tbu,
0x00000000);
}
--
1.7.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] TBL register permissions for PPC
2010-03-26 0:31 ` Dmitry Ilyevsky
@ 2010-03-26 1:15 ` Alexander Graf
2010-03-26 22:42 ` Aurelien Jarno
1 sibling, 0 replies; 9+ messages in thread
From: Alexander Graf @ 2010-03-26 1:15 UTC (permalink / raw)
To: Dmitry Ilyevsky; +Cc: qemu-devel
On 26.03.2010, at 01:31, Dmitry Ilyevsky wrote:
> On Thu, Mar 25, 2010 at 10:53 AM, Alexander Graf <agraf@suse.de> wrote:
>>
>> On 24.03.2010, at 22:56, Dmitry Ilyevsky wrote:
>>
>>>
>>> Hello All,
>>>
>>> Please review patch for TBL SPR read access for generic PPC.
>>>
>>> Description:
>>>
>>> POWER specification docs define TBL/TBU SPRs as readable in user and privileged modes. Therefore SPRs permissions were changed in gen_tbl function in target-ppc/translate_init.c file.
>>>
>>> Testing:
>>>
>>> Tested with vxworks-6.2 bsp and OS on custom qemu board that includes ppc405 emulated core
>>
>> A couple of comments to this patch.
>>
>> 1) Please don't top-post.
>> 2) Always put a Signed-off-by: in the patch
>> 3) Put the patch description into the patch, so git knows what to do with it
>> 4) Don't use html features in mail :-)
>>
>> The patch looks good otherwise.
>>
>>
>> Alex
>>
>>
>
> Corrected.
>
> Thanks,
> Dmitry I.
> <0001-Generic-PowerPC-TBL.patch>
Acked-by: Alexander Graf <agraf@suse.de>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] TBL register permissions for PPC
2010-03-26 0:31 ` Dmitry Ilyevsky
2010-03-26 1:15 ` Alexander Graf
@ 2010-03-26 22:42 ` Aurelien Jarno
1 sibling, 0 replies; 9+ messages in thread
From: Aurelien Jarno @ 2010-03-26 22:42 UTC (permalink / raw)
To: Dmitry Ilyevsky; +Cc: Alexander Graf, qemu-devel
On Fri, Mar 26, 2010 at 03:31:25AM +0300, Dmitry Ilyevsky wrote:
> On Thu, Mar 25, 2010 at 10:53 AM, Alexander Graf <agraf@suse.de> wrote:
> >
> > On 24.03.2010, at 22:56, Dmitry Ilyevsky wrote:
> >
> >>
> >> Hello All,
> >>
> >> Please review patch for TBL SPR read access for generic PPC.
> >>
> >> Description:
> >>
> >> POWER specification docs define TBL/TBU SPRs as readable in user and privileged modes. Therefore SPRs permissions were changed in gen_tbl function in target-ppc/translate_init.c file.
> >>
> >> Testing:
> >>
> >> Tested with vxworks-6.2 bsp and OS on custom qemu board that includes ppc405 emulated core
> >
> > A couple of comments to this patch.
> >
> > 1) Please don't top-post.
> > 2) Always put a Signed-off-by: in the patch
> > 3) Put the patch description into the patch, so git knows what to do with it
> > 4) Don't use html features in mail :-)
> >
> > The patch looks good otherwise.
> >
> >
> > Alex
> >
> >
>
> Corrected.
>
> Thanks,
> Dmitry I.
Thanks, applied.
> From b5846b7df136c1eff7df8dada8800c81e1799cf4 Mon Sep 17 00:00:00 2001
> From: Dmitry Ilyevsky <ilyevsky@gmail.com>
> Date: Fri, 26 Mar 2010 03:25:36 +0300
> Subject: Generic PowerPC TBL
>
> Time base SPRs TBL/TBU should be accessible in user/priv modes for reading as specified in POWER ISA documentation. Therefore SPRs permissions were changed in gen_tbl function.
>
> Signed-off-by: Dmitry Ilyevsky <ilyevsky@gmail.com>
> ---
> target-ppc/translate_init.c | 8 ++++----
> 1 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index db4dc17..e8eadf4 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -777,16 +777,16 @@ static void gen_tbl (CPUPPCState *env)
> &spr_read_tbl, SPR_NOACCESS,
> 0x00000000);
> spr_register(env, SPR_TBL, "TBL",
> - SPR_NOACCESS, SPR_NOACCESS,
> - SPR_NOACCESS, &spr_write_tbl,
> + &spr_read_tbl, SPR_NOACCESS,
> + &spr_read_tbl, &spr_write_tbl,
> 0x00000000);
> spr_register(env, SPR_VTBU, "TBU",
> &spr_read_tbu, SPR_NOACCESS,
> &spr_read_tbu, SPR_NOACCESS,
> 0x00000000);
> spr_register(env, SPR_TBU, "TBU",
> - SPR_NOACCESS, SPR_NOACCESS,
> - SPR_NOACCESS, &spr_write_tbu,
> + &spr_read_tbu, SPR_NOACCESS,
> + &spr_read_tbu, &spr_write_tbu,
> 0x00000000);
> }
>
> --
> 1.7.0
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2010-03-26 22:42 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2009-12-01 18:33 [Qemu-devel] TBL register permissions for PPC Dima Ilyevsky
2009-12-01 19:28 ` Krumme, Chris
2009-12-01 23:23 ` Alexander Graf
2009-12-01 23:35 ` malc
2010-03-24 21:56 ` Dmitry Ilyevsky
2010-03-25 7:53 ` Alexander Graf
2010-03-26 0:31 ` Dmitry Ilyevsky
2010-03-26 1:15 ` Alexander Graf
2010-03-26 22:42 ` Aurelien Jarno
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