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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id r7-20020aa78b87000000b006e48b04d8c0sm4416024pfd.64.2024.02.26.11.16.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Feb 2024 11:16:47 -0800 (PST) Message-ID: <4aba8c00-90c0-4b01-b6bb-fadda72acfef@linaro.org> Date: Mon, 26 Feb 2024 09:16:43 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 04/21] target/arm: Implement ALLINT MSR (immediate) To: Jinjie Ruan , peter.maydell@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20240223103221.1142518-1-ruanjinjie@huawei.com> <20240223103221.1142518-5-ruanjinjie@huawei.com> <9b20584a-3c4c-47a2-bf42-f8d7d4eabd9f@linaro.org> <138ddc99-f6f4-9907-a1c2-6b2b88bd79d0@huawei.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <138ddc99-f6f4-9907-a1c2-6b2b88bd79d0@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/25/24 16:22, Jinjie Ruan wrote: > > > On 2024/2/24 3:03, Richard Henderson wrote: >> On 2/23/24 00:32, Jinjie Ruan via wrote: >>> Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary >>> to ALLINT. Avoid the unconditional write to pc and use raise_exception_ra >>> to unwind. >>> >>> Signed-off-by: Jinjie Ruan >>> --- >>> v3: >>> - Remove EL0 check in allint_check(). >>> - Add TALLINT check for EL1 in allint_check(). >>> - Remove unnecessarily arm_rebuild_hflags() in msr_i_allint helper. >>> --- >>>   target/arm/tcg/a64.decode      |  1 + >>>   target/arm/tcg/helper-a64.c    | 24 ++++++++++++++++++++++++ >>>   target/arm/tcg/helper-a64.h    |  1 + >>>   target/arm/tcg/translate-a64.c | 10 ++++++++++ >>>   4 files changed, 36 insertions(+) >>> >>> diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode >>> index 8a20dce3c8..3588080024 100644 >>> --- a/target/arm/tcg/a64.decode >>> +++ b/target/arm/tcg/a64.decode >>> @@ -207,6 +207,7 @@ MSR_i_DIT       1101 0101 0000 0 011 0100 .... 010 >>> 11111 @msr_i >>>   MSR_i_TCO       1101 0101 0000 0 011 0100 .... 100 11111 @msr_i >>>   MSR_i_DAIFSET   1101 0101 0000 0 011 0100 .... 110 11111 @msr_i >>>   MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i >>> +MSR_i_ALLINT    1101 0101 0000 0 001 0100 .... 000 11111 @msr_i >> >> Decode is incorrect either here, or in trans_MSR_i_ALLINT, because CRm >> != '000x' is UNDEFINED. >> >> MSR_i_ALLINT    1101 0101 0000 0 001 0100 000 imm:1 000 11111 >> >> is perhaps the clearest implementation. >> >>> +static void allint_check(CPUARMState *env, uint32_t op, >>> +                       uint32_t imm, uintptr_t ra) >>> +{ >>> +    /* ALLINT update to PSTATE. */ >>> +    if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) && >>> +        (arm_hcrx_el2_eff(env) & HCRX_TALLINT)) { >>> +        raise_exception_ra(env, EXCP_UDEF, >>> +                           syn_aa64_sysregtrap(0, extract32(op, 0, 3), >>> +                                               extract32(op, 3, 3), 4, >>> +                                               imm, 0x1f, 0), >>> +                           exception_target_el(env), ra); >>> +    } >>> +} >>> + >>> +void HELPER(msr_i_allint)(CPUARMState *env, uint32_t imm) >>> +{ >>> +    allint_check(env, 0x8, imm, GETPC()); >> >> As previously noted, the check for MSR_i only applies to imm==1, not 0. > > Sorry! The hardware manual I looked at didn't say this. In DDI0487J.a, C6.2.229 MSR (immediate), it is present in the pseudocode when PSTATEField_ALLINT if (PSTATE.EL == EL1 && IsHCRXEL2Enabled() && HCRX_EL2.TALLINT == '1' && CRm<0> == '1') then AArch64.SystemAccessTrap(EL2, 0x18); PSTATE.ALLINT = CRm<0>; In D19.2.49 HCRX_EL2, it is present as text for the description of TALLINT. r~