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([2001:8004:2728:2ad6:e985:c1c8:a4fc:508]) by smtp.gmail.com with ESMTPSA id jj7-20020a170903048700b001d472670a30sm3695512plb.162.2024.01.12.14.41.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Jan 2024 14:41:06 -0800 (PST) Message-ID: <4b0847ec-467f-4fcb-8deb-01ec435d82ad@linaro.org> Date: Sat, 13 Jan 2024 09:40:59 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 08/13] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl) Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, max.chou@sifive.com References: <20240112213812.173521-1-dbarboza@ventanamicro.com> <20240112213812.173521-9-dbarboza@ventanamicro.com> From: Richard Henderson In-Reply-To: <20240112213812.173521-9-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/13/24 08:38, Daniel Henrique Barboza wrote: > Use the new 'vlenb' CPU config to validate fractional LMUL. The original > comparison is done with 'vlen' and 'sew', both in bits. Use sew/8, or > sew in bytes, to do a direct comparison with vlenb. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/vector_helper.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index cb944229b0..0c1a485d1e 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -45,9 +45,12 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > xlen - 1 - R_VTYPE_RESERVED_SHIFT); > > if (lmul & 4) { > - /* Fractional LMUL - check LMUL * VLEN >= SEW */ > - if (lmul == 4 || > - cpu->cfg.vlen >> (8 - lmul) < sew) { > + /* > + * Fractional LMUL - check LMUL * VLEN >= SEW, or > + * vlen >> (8 - lmul) < sew. We have 'vlenb', so > + * compare it with sew in bytes. > + */ > + if (lmul == 4 || cpu->cfg.vlenb >> (8 - lmul) < (sew << 3)) { You're shifting sew the wrong direction. But better to simply adjust the vlenb shift: - cpu->cfg.vlen >> (8 - lmul) < sew + cpu->cfg.vlenb >> (8 - 3 - lmul) < sew r~