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[176.172.55.165]) by smtp.gmail.com with ESMTPSA id p5-20020a05600c358500b004053a6b8c41sm11195398wmq.12.2023.10.24.00.08.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Oct 2023 00:08:07 -0700 (PDT) Message-ID: <4b2e68dd-db49-4041-ee5a-ae2b836bd255@linaro.org> Date: Tue, 24 Oct 2023 09:08:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v6 02/10] hw/fsi: Introduce IBM's scratchpad Content-Language: en-US To: Ninad Palsule , qemu-devel@nongnu.org, clg@kaod.org, peter.maydell@linaro.org, andrew@codeconstruct.com.au, joel@jms.id.au, pbonzini@redhat.com, marcandre.lureau@redhat.com, berrange@redhat.com, thuth@redhat.com, lvivier@redhat.com Cc: qemu-arm@nongnu.org, Andrew Jeffery References: <20231021211720.3571082-1-ninad@linux.ibm.com> <20231021211720.3571082-3-ninad@linux.ibm.com> <957bc5db-53aa-6946-edf3-3b728a52b660@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.339, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 23/10/23 19:08, Ninad Palsule wrote: > Hello Philippe, > > On 10/23/23 10:00, Philippe Mathieu-Daudé wrote: >> On 21/10/23 23:17, Ninad Palsule wrote: >>> This is a part of patchset where scratchpad is introduced. >>> >>> The scratchpad provides a set of non-functional registers. The firmware >>> is free to use them, hardware does not support any special management >>> support. The scratchpad registers can be read or written from LBUS >>> slave. >>> >>> In this model, The LBUS device is parent for the scratchpad. >>> >>> Signed-off-by: Andrew Jeffery >>> Signed-off-by: Ninad Palsule >>> --- >>> v2: >>> - Incorporated Joel's review comments. >>> v5: >>> - Incorporated review comments by Cedric. >>> v6: >>> - Incorporated review comments by Daniel. >>> --- >>>   meson.build                        |  1 + >>>   hw/fsi/trace.h                     |  1 + >>>   include/hw/fsi/engine-scratchpad.h | 32 ++++++++++ >>>   include/hw/fsi/fsi.h               | 16 +++++ >>>   hw/fsi/engine-scratchpad.c         | 93 ++++++++++++++++++++++++++++++ >>>   hw/fsi/Kconfig                     |  4 ++ >>>   hw/fsi/meson.build                 |  1 + >>>   hw/fsi/trace-events                |  2 + >>>   8 files changed, 150 insertions(+) >>>   create mode 100644 hw/fsi/trace.h >>>   create mode 100644 include/hw/fsi/engine-scratchpad.h >>>   create mode 100644 include/hw/fsi/fsi.h >>>   create mode 100644 hw/fsi/engine-scratchpad.c >>>   create mode 100644 hw/fsi/trace-events >> >> >>> diff --git a/include/hw/fsi/fsi.h b/include/hw/fsi/fsi.h >>> new file mode 100644 >>> index 0000000000..e65f26f17b >>> --- /dev/null >>> +++ b/include/hw/fsi/fsi.h >>> @@ -0,0 +1,16 @@ >>> +/* >>> + * SPDX-License-Identifier: GPL-2.0-or-later >>> + * Copyright (C) 2023 IBM Corp. >>> + * >>> + * IBM Flexible Service Interface >>> + */ >>> +#ifndef FSI_FSI_H >>> +#define FSI_FSI_H >>> + >>> +/* Bitwise operations at the word level. */ >>> +#define BE_BIT(x)                          BIT(31 - (x)) >>> +#define GENMASK(t, b) \ >>> +    (((1ULL << ((t) + 1)) - 1) & ~((1ULL << (b)) - 1)) >> >> Please use MAKE_64BIT_MASK() from "qemu/bitops.h". > > The GENMASK and MAKE_64BIT_MASK macros are invoke differently. > > GENMASK is invoked with bit t and bit b (t:b) and it provides the mask and > > MAKE_64BIT_MASK uses shift and length. Don't we have: #define GENMASK(t, b) MAKE_64BIT_MASK(t, b - t + 1) ? > Thanks for the review. > > Regards, > > Ninad > > >>> +#define BE_GENMASK(t, b)                   GENMASK(BE_BIT(t), >>> BE_BIT(b)) >>> + >>> +#endif >>