From: Richard Henderson <richard.henderson@linaro.org>
To: Richard Bagley <rbagley@ventanamicro.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
dbarboza@ventanamicro.com
Subject: Re: [PATCH] disas/riscv: Further correction to LUI disassembly
Date: Mon, 31 Jul 2023 13:37:21 -0700 [thread overview]
Message-ID: <4b38596d-1db6-e03f-8b42-65c4464132ab@linaro.org> (raw)
In-Reply-To: <20230731183320.410922-1-rbagley@ventanamicro.com>
On 7/31/23 11:33, Richard Bagley wrote:
> The recent commit 36df75a0a9 corrected one aspect of LUI disassembly
> by recovering the immediate argument from the result of LUI with a
> shift right by 12. However, the shift right will left-fill with the
> sign. By applying a mask we recover an unsigned representation of the
> 20-bit field (which includes a sign bit).
Why would you want that? Surely
lui r1, -1
is more accurate than
lui r1, 0xfffff
r~
next prev parent reply other threads:[~2023-07-31 20:38 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-31 18:33 [PATCH] disas/riscv: Further correction to LUI disassembly Richard Bagley
2023-07-31 20:37 ` Richard Henderson [this message]
2023-08-07 22:01 ` Richard Bagley
2023-08-07 22:59 ` Richard Henderson
2023-08-10 15:31 ` Andrew Jones
2023-08-10 16:12 ` Palmer Dabbelt
2023-08-10 16:27 ` Andrew Jones
2023-08-11 8:25 ` Andrew Jones
2023-08-11 11:55 ` Andrew Jones
2024-03-08 0:08 ` Richard Bagley
2024-03-09 4:22 ` Richard Bagley
2024-03-09 12:01 ` Andrew Jones
2024-03-11 18:56 ` Richard Bagley
2024-03-11 20:00 ` Richard Bagley
2024-03-12 11:09 ` Andrew Jones
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