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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id l4-20020a05622a174400b003f532993912sm428797qtk.74.2023.05.15.06.15.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 May 2023 06:15:34 -0700 (PDT) Message-ID: <4b41c86f-99e5-96e8-6fba-692f73006dcb@redhat.com> Date: Mon, 15 May 2023 15:15:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [RFC PATCH v3 10/10] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2 Content-Language: en-US To: Mostafa Saleh , qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org References: <20230401104953.1325983-1-smostafa@google.com> <20230401104953.1325983-11-smostafa@google.com> From: Eric Auger In-Reply-To: <20230401104953.1325983-11-smostafa@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -58 X-Spam_score: -5.9 X-Spam_bar: ----- X-Spam_report: (-5.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.811, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Mostafa, On 4/1/23 12:49, Mostafa Saleh wrote: > As everything is in place, we can use a new system property to > advertise which stage is supported and remove bad_ste from STE > stage2 config. > > The property added arm-smmuv3.stage can have 3 values: > - "1": Stage-1 only is advertised. > - "2": Stage-2 only is advertised. > - "all": Stage-1 + Stage-2 are supported, which is not implemented in > this patch series. > > If not passed or an unsupported value is passed, it will default to > stage-1. > > Advertise VMID16. > > Don't try to decode CD, if stage-2 is configured. > > Signed-off-by: Mostafa Saleh > --- > Changes in v2: > - Squash knob patch with stage-2 enable patch. > - Don't try to decode CD, if stage-2 is configured. > --- > hw/arm/smmuv3.c | 34 +++++++++++++++++++++++++--------- > include/hw/arm/smmuv3.h | 1 + > 2 files changed, 26 insertions(+), 9 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 826aacf8b1..22b5613d4c 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -21,6 +21,7 @@ > #include "hw/irq.h" > #include "hw/sysbus.h" > #include "migration/vmstate.h" > +#include "hw/qdev-properties.h" > #include "hw/qdev-core.h" > #include "hw/pci/pci.h" > #include "cpu.h" > @@ -248,14 +249,20 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info) > > static void smmuv3_init_regs(SMMUv3State *s) > { > - /** > - * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID, > - * multi-level stream table > + /* > + * Based on sys property, the stages supported in smmu will be advertised. > + * At the moment "all" is not supported and default to stage-1. > */ > - s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supported */ > + if (s->stage && !strcmp("2", s->stage)) { > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S2P, 1); > + } else { > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); > + } > + > s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */ > s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */ > s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */ > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, VMID16, 1); /* 16-bit VMID */ > s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */ > s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */ > /* terminated transaction will always be aborted/error returned */ > @@ -458,10 +465,6 @@ static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste) > goto bad_ste; > } > > - /* This is still here as stage 2 has not been fully enabled yet. */ > - qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n"); > - goto bad_ste; > - > return 0; > > bad_ste: > @@ -740,7 +743,7 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg, > return ret; > } > > - if (cfg->aborted || cfg->bypassed) { > + if (cfg->aborted || cfg->bypassed || (cfg->stage == 2)) { > return 0; > } > > @@ -1809,6 +1812,18 @@ static const VMStateDescription vmstate_smmuv3 = { > } > }; > > +static Property smmuv3_properties[] = { > + /* > + * Stages of translation advertised. > + * "1": Stage 1 > + * "2": Stage 2 > + * "all": Stage 1 + Stage 2 I don't think you should talk about 'all' at the moment. Besides Reviewed-by: Eric Auger Eric > + * Defaults to stage 1 > + */ > + DEFINE_PROP_STRING("stage", SMMUv3State, stage), > + DEFINE_PROP_END_OF_LIST() > +}; > + > static void smmuv3_instance_init(Object *obj) > { > /* Nothing much to do here as of now */ > @@ -1825,6 +1840,7 @@ static void smmuv3_class_init(ObjectClass *klass, void *data) > &c->parent_phases); > c->parent_realize = dc->realize; > dc->realize = smmu_realize; > + device_class_set_props(dc, smmuv3_properties); > } > > static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, > diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h > index 6031d7d325..d183a62766 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -62,6 +62,7 @@ struct SMMUv3State { > > qemu_irq irq[4]; > QemuMutex mutex; > + char *stage; > }; > > typedef enum {