From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34474) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUAvp-0004gB-J1 for qemu-devel@nongnu.org; Mon, 01 Aug 2016 06:58:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bUAvm-0004nr-GA for qemu-devel@nongnu.org; Mon, 01 Aug 2016 06:58:49 -0400 Received: from mail-io0-x241.google.com ([2607:f8b0:4001:c06::241]:34132) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUAvm-0004nR-7I for qemu-devel@nongnu.org; Mon, 01 Aug 2016 06:58:46 -0400 Received: by mail-io0-x241.google.com with SMTP id g86so13774926ioj.1 for ; Mon, 01 Aug 2016 03:58:46 -0700 (PDT) Sender: Paolo Bonzini References: <1469974685-4144-1-git-send-email-peterx@redhat.com> From: Paolo Bonzini Message-ID: <4b4dd69d-81fa-d74c-86a9-1723bbd23c95@redhat.com> Date: Mon, 1 Aug 2016 12:58:42 +0200 MIME-Version: 1.0 In-Reply-To: <1469974685-4144-1-git-send-email-peterx@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH for 2.8?] x86: ioapic: ignore level irq during processing List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Xu , qemu-devel@nongnu.org Cc: mst@redhat.com On 31/07/2016 16:18, Peter Xu wrote: > For level triggered interrupts, we will get Remote IRR bit cleared after > guest kernel finished processing specific request. Before that, we > should ignore the same interrupt from triggering again. > > Signed-off-by: Peter Xu > --- > > I discovered this during debugging some IR issues. Only did very > minimum test with e1000, but IIUC this should be the correct behavior > for level triggered interrupts, and before that we might be sending > some extra interrupts to guest (while we should not). > > hw/intc/ioapic.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c > index 2d3282a..350f761 100644 > --- a/hw/intc/ioapic.c > +++ b/hw/intc/ioapic.c > @@ -129,9 +129,15 @@ static void ioapic_service(IOAPICCommonState *s) > } > continue; > } > -#else > - (void)coalesce; > #endif > + > + if (coalesce) { > + /* We are level triggered interrupts, and the > + * guest should be still working on previous one, > + * so skip it. */ > + continue; > + } > + > /* No matter whether IR is enabled, we translate > * the IOAPIC message into a MSI one, and its > * address space will decide whether we need a > The patch is okay for 2.7, as it matches what is done in the KVM split-irqchip case. Paolo