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Fri, 15 Oct 2021 10:05:52 -0700 (PDT) Subject: Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20211015065500.3850513-1-frank.chang@sifive.com> <20211015065500.3850513-3-frank.chang@sifive.com> From: Richard Henderson Message-ID: <4b718269-b222-c08f-ca72-656bacc31331@linaro.org> Date: Fri, 15 Oct 2021 10:05:50 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211015065500.3850513-3-frank.chang@sifive.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chih-Min Chao , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/14/21 11:54 PM, frank.chang@sifive.com wrote: > From: Chih-Min Chao > > The sNaN propagation behavior has been changed since > cd20cee7 inhttps://github.com/riscv/riscv-isa-manual > > Signed-off-by: Chih-Min Chao > --- > target/riscv/fpu_helper.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > index 8700516a14c..1472ead2528 100644 > --- a/target/riscv/fpu_helper.c > +++ b/target/riscv/fpu_helper.c > @@ -174,14 +174,14 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) > { > float32 frs1 = check_nanbox_s(rs1); > float32 frs2 = check_nanbox_s(rs2); > - return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status)); > + return nanbox_s(float32_minnum_noprop(frs1, frs2, &env->fp_status)); > } Don't you need to conditionalize behaviour on the isa revision? r~