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Fri, 8 Mar 2024 15:17:08 +0000 (GMT) Message-ID: <4b73cdf8-ce5c-424b-b81d-73c1fd72a385@linux.ibm.com> Date: Fri, 8 Mar 2024 10:17:07 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/5] hw/ppc: SPI controller model - registers implementation Content-Language: en-US From: Stefan Berger To: Chalapathi V , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, saif.abrar@linux.vnet.ibm.com References: <20240207160833.3437779-1-chalapathi.v@linux.ibm.com> <20240207160833.3437779-3-chalapathi.v@linux.ibm.com> <6ab8bb8e-5126-4322-bb91-6709e46c444a@linux.ibm.com> In-Reply-To: <6ab8bb8e-5126-4322-bb91-6709e46c444a@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: E-sLS95uWSw5Z3a34aezIOW9YY4ZmGSz X-Proofpoint-GUID: EkjZfK3VXOcw_i_Zx7wBghLGeeN1P3xJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-08_08,2024-03-06_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 spamscore=0 clxscore=1015 adultscore=0 malwarescore=0 phishscore=0 mlxlogscore=821 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2403080123 Received-SPF: pass client-ip=148.163.158.5; envelope-from=stefanb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/7/24 13:54, Stefan Berger wrote: > > > On 2/7/24 11:08, Chalapathi V wrote: >> SPI controller device model supports a connection to a single SPI >> responder. >> This provide access to SPI seeproms, TPM, flash device and an ADC >> controller. >> >> All SPI function control is mapped into the SPI register space to >> enable full >> control by firmware. In this commit SPI configuration component is >> modelled >> which contains all SPI configuration and status registers as well as >> the hold >> registers for data to be sent or having been received. >> >> Signed-off-by: Chalapathi V > >> +    case SEQUENCER_OPERATION_REG: >> +        for (int i = 0; i < SPI_CONTROLLER_REG_SIZE; i++) { >> +            sc->sequencer_operation_reg[i] = >> +                 (val & PPC_BITMASK(i * 8 , i * 8 + 7)) >> (63 - (i * >> 8 + 7)); > > To me it would be more obvious if you used a mask here like this: > > mask = PPC_BIT_MASK(0, 7); > mask = (0xff << 56); > > for (...) { >     sc->sequencer_operation_reg[i] = (val & mask) >> (56 - i * 8); >     mask >>= 8; > } > Actually simpler and even this masking is not necessary: for (...) { sc->sequencer_operation_reg[i] = (val >> (56 - i * 8)) & 0xff; }