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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f259f8273sm19792375f8f.89.2025.02.20.02.31.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Feb 2025 02:31:38 -0800 (PST) Message-ID: <4b7cfa82-c730-43af-ab47-53f20131104a@redhat.com> Date: Thu, 20 Feb 2025 11:31:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC 0/2] hw/vfio/pci: Prevent BARs from being dma mapped in d3hot state Content-Language: en-US To: Alex Williamson Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, clg@redhat.com, zhenzhong.duan@intel.com References: <20250219175941.135390-1-eric.auger@redhat.com> <20250219115844.062c5513.alex.williamson@redhat.com> <20250219141945.5e74c7f3.alex.williamson@redhat.com> From: Eric Auger In-Reply-To: <20250219141945.5e74c7f3.alex.williamson@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.191, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Alex, On 2/19/25 10:19 PM, Alex Williamson wrote: > On Wed, 19 Feb 2025 11:58:44 -0700 > Alex Williamson wrote: > >> On Wed, 19 Feb 2025 18:58:58 +0100 >> Eric Auger wrote: >> >>> Since kernel commit: >>> 2b2c651baf1c ("vfio/pci: Invalidate mmaps and block the access >>> in D3hot power state") >>> any attempt to do an mmap access to a BAR when the device is in d3hot >>> state will generate a fault. >>> >>> On system_powerdown, if the VFIO device is translated by an IOMMU, >>> the device is moved to D3hot state and then the vIOMMU gets disabled >>> by the guest. As a result of this later operation, the address space is >>> swapped from translated to untranslated. When re-enabling the aliased >>> regions, the RAM regions are dma-mapped again and this causes DMA_MAP >>> faults when attempting the operation on BARs. >>> >>> To avoid doing the remap on those BARs, we compute whether the >>> device is in D3hot state and if so, skip the DMA MAP. >> Thinking on this some more, QEMU PCI code already manages the device >> BARs appearing in the address space based on the memory enable bit in >> the command register. Should we do the same for PM state? >> >> IOW, the device going into low power state should remove the BARs from >> the AddressSpace and waking the device should re-add them. The BAR DMA >> mapping should then always be consistent, whereas here nothing would >> remap the BARs when the device is woken. >> >> I imagine we'd need an interface to register the PM capability with the >> core QEMU PCI code, where address space updates are performed relative >> to both memory enable and power status. There might be a way to >> implement this just for vfio-pci devices by toggling the enable state >> of the BAR mmaps relative to PM state, but doing it at the PCI core >> level seems like it'd provide behavior more true to physical hardware. > I took a stab at this approach here, it doesn't obviously break > anything in my configs, but I haven't yet tried to reproduce this exact > scenario. > > https://gitlab.com/alex.williamson/qemu/-/tree/pci-pm-power-state So if I understand correctly the BAR regions will disappear upon the config cmd write in vfio_sub_page_bar_update_mapping(). Is that correct? I will give it a try on my setup... > > There's another pm_cap on the PCIExpressDevice that needs to be > consolidated as well, once I do some research to figure out why a > non-express capability is tracked only by express devices and what > they're doing with it. Thanks, I am not sure I get this last point though. Thanks Eric > > Alex >