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[149.14.88.106]) by smtp.gmail.com with ESMTPSA id e7-20020ad450c7000000b005dd8b934592sm5320840qvq.42.2023.03.30.03.09.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Mar 2023 03:09:09 -0700 (PDT) Message-ID: <4ba6df70-6fb9-6ee8-d6b6-0c7e403c34d7@redhat.com> Date: Thu, 30 Mar 2023 12:09:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Rob Landley , Nathan Chancellor Cc: Jiaxun Yang , qemu-devel@nongnu.org, balaton@eik.bme.hu, Bernhard Beschow , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= , Peter Maydell References: <20230223161958.48696-1-jiaxun.yang@flygoat.com> <20230320165821.GA4064187@dev-arch.thelio-3990X> <037d00b7-9df9-e888-a4d7-235e6d08f784@landley.net> <89504c25-5265-d6c5-6e48-dcdc0be43ea0@linaro.org> From: Thomas Huth Subject: Re: [PATCH] hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR In-Reply-To: <89504c25-5265-d6c5-6e48-dcdc0be43ea0@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 29/03/2023 18.07, Philippe Mathieu-Daudé wrote: > On 29/3/23 18:09, Rob Landley wrote: >> On 3/28/23 12:02, Philippe Mathieu-Daudé wrote: >>> On 20/3/23 17:58, Nathan Chancellor wrote: >>>> On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote: >>>>> On 23/2/23 17:19, Jiaxun Yang wrote: >>>>>> 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE >>>>>> MemoryRegionOps") converted CFGADDR/CFGDATA registers to use >>>>>> PCI_HOST_BRIDGE's >>>>>> accessor facility and enabled byte swap for both CFGADDR/CFGDATA >>>>>> register. >>>>>> >>>>>> However CFGADDR as a ISD internal register is not controled by MByteSwap >>>>>> bit, it follows endian of all other ISD register, which means it ties to >>>>>> little endian. >>>>>> >>>>>> Move mapping of CFGADDR out of gt64120_update_pci_cfgdata_mapping to >>>>>> disable >>>>>> endian-swapping. >>>>>> >>>>>> This should fix some recent reports about poweroff hang. >>>>>> >>>>>> Fixes: 145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using >>>>>> PCI_HOST_BRIDGE MemoryRegionOps") >>>>>> Signed-off-by: Jiaxun Yang >>>>>> --- >>>>>>     hw/pci-host/gt64120.c | 18 ++++++------------ >>>>>>     1 file changed, 6 insertions(+), 12 deletions(-) >>>>> >>>>> So this works on little-endian hosts, but fails on >>>>> big-endian ones :( >>>>> >>>>> I.e. on Linux we have early_console_write() -> prom_putchar() >>>>> looping: >>>>> >>>>> IN: prom_putchar >>>>> 0x8010fab8:  lbu    v0,0(v1) >>>>> 0x8010fabc:  andi    v0,v0,0x20 >>>>> 0x8010fac0:  beqz    v0,0x8010fab8 >>>>> 0x8010fac4:  andi    v0,a0,0xff >>>>> >>>>> gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 >>>>> gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 >>>>> gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 >>>>> gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 >>>>> gt64120: Illegal register read reg:0x3fc size:4 value:0x00000000 >>>>> ... >>>>> >>>> >>>> Is there going to be a new version of this patch or a different solution >>>> to the poweroff hang then? I am still seeing that with tip of tree QEMU >>>> and I see 8.0.0-rc0 has been tagged; I would hate for this to end up in >>>> a release version. >>> >>> I couldn't work a fix, however I ran our (new) tests on merge >>> commit 3db29dcac2 which is before the offending commit 145e2198d749, >>> and they fail. So I suppose Malta on big-endian host is badly broken >>> since quite some time. Thus clearly nobody tests/runs Malta there. >> >> I test/run malta with the mips and mipsel binaries at >> https://landley.net/toybox/downloads/binaries/mkroot/0.8.9/ but I'm still >> locally applying the first patch I saw to fix this (attached) until upstream >> sorts itself out. >> >> Works fine for me. Somebody said it was the wrong fix but I don't remember >> why... > > This is a correct /partial/ fix. With this patch, Malta works on little > endian hosts. No luck with big-endian hosts, but this was broken > previous to 3db29dcac2 rework, so apparently not a big deal ¯\_(ツ)_/¯ I've bisected now on a big endian s390x machine, and it looks like it has been broken here: 0c8427baf0f66bdaecae41891304f6e15242e682 is the first bad commit commit 0c8427baf0f66bdaecae41891304f6e15242e682 Author: Jiaxun Yang Date: Wed Oct 26 21:18:21 2022 +0200 hw/mips/malta: Use bootloader helper to set BAR registers ... we should maybe really run a selected list of avocado jobs on a big endian host (either .travis-ci.yml or the gitlab-CI custom runner?) to avoid such regressions? Thomas