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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id c1sm8030081pfa.51.2020.02.14.12.27.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Feb 2020 12:27:09 -0800 (PST) Subject: Re: [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200214175116.9164-1-peter.maydell@linaro.org> <20200214175116.9164-13-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <4bb63598-4eef-18a8-9dbc-4f6652ba12e2@linaro.org> Date: Fri, 14 Feb 2020 12:27:07 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200214175116.9164-13-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/14/20 9:51 AM, Peter Maydell wrote: > + /* > + * DBGDIDR is a bit complicated because the kernel doesn't > + * provide an accessor for it in 64-bit mode, which is what this > + * scratch VM is in, and there's no architected "64-bit sysreg > + * which reads the same as the 32-bit register" the way there is > + * for other ID registers. Instead we synthesize a value from the > + * AArch64 ID_AA64DFR0, the same way the kernel code in > + * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. > + * We only do this if the CPU supports AArch32 at EL1. > + */ > + if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) { > + int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS); > + int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS); > + int ctx_cmps = > + FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); > + int version = 6; /* ARMv8 debug architecture */ > + bool has_el3 = > + !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); > + uint32_t dbgdidr = 0; > + > + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); > + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); > + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); > + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); > + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); > + dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); > + dbgdidr |= (1 << 16); /* RES1 bit */ I see the RES1 bit as 15. Otherwise, Reviewed-by: Richard Henderson r~