From: Richard Henderson <richard.henderson@linaro.org>
To: Stafford Horne <shorne@gmail.com>,
QEMU Development <qemu-devel@nongnu.org>
Cc: Openrisc <openrisc@lists.librecores.org>
Subject: Re: [PATCH v2 07/11] target/openrisc: Add interrupted CPU to log
Date: Mon, 4 Jul 2022 15:34:52 +0530 [thread overview]
Message-ID: <4bfc20ec-962b-2017-f2ba-26cd65bd3d9f@linaro.org> (raw)
In-Reply-To: <20220703212823.10067-8-shorne@gmail.com>
On 7/4/22 02:58, Stafford Horne wrote:
> When we are tracing it's helpful to know which CPU's are getting
> interrupted, att that detail to the log line.
"at".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> target/openrisc/interrupt.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
> index e5724f5371..c31c6f12c4 100644
> --- a/target/openrisc/interrupt.c
> +++ b/target/openrisc/interrupt.c
> @@ -83,7 +83,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
> [EXCP_TRAP] = "TRAP",
> };
>
> - qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
> + qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n",
> + cs->cpu_index,
> + int_name[exception]);
>
> hwaddr vect_pc = exception << 8;
> if (env->cpucfgr & CPUCFGR_EVBARP) {
next prev parent reply other threads:[~2022-07-04 10:06 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-03 21:28 [PATCH v2 00/11] OpenRISC Virtual Machine Stafford Horne
2022-07-03 21:28 ` [PATCH v2 01/11] hw/openrisc: Split re-usable boot time apis out to boot.c Stafford Horne
2022-07-03 21:28 ` [PATCH v2 02/11] target/openrisc: Fix memory reading in debugger Stafford Horne
2022-07-04 10:01 ` Richard Henderson
2022-07-03 21:28 ` [PATCH v2 03/11] goldfish_rtc: Add endianness property Stafford Horne
2022-07-04 2:50 ` Anup Patel
2022-07-04 9:59 ` Richard Henderson
2022-07-04 10:16 ` Laurent Vivier
2022-07-04 10:21 ` Richard Henderson
2022-07-04 10:23 ` Laurent Vivier
2022-07-04 20:40 ` Stafford Horne
2022-07-05 0:53 ` Jason A. Donenfeld
2022-07-04 20:32 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 04/11] hw/openrisc: Add the OpenRISC virtual machine Stafford Horne
2022-07-03 21:28 ` [PATCH v2 05/11] hw/openrisc: Add PCI bus support to virt Stafford Horne
2022-07-03 21:28 ` [PATCH v2 06/11] hw/openrisc: Initialize timer time at startup Stafford Horne
2022-07-04 10:03 ` Richard Henderson
2022-07-04 20:32 ` [PATCH v2 06/11] hw/openrisc: Initialize timer time at startupi Stafford Horne
2022-07-03 21:28 ` [PATCH v2 07/11] target/openrisc: Add interrupted CPU to log Stafford Horne
2022-07-04 10:04 ` Richard Henderson [this message]
2022-07-04 20:26 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 08/11] target/openrisc: Enable MTTCG Stafford Horne
2022-07-04 10:07 ` Richard Henderson
2022-07-04 20:31 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 09/11] target/openrisc: Interrupt handling fixes Stafford Horne
2022-07-04 10:20 ` Richard Henderson
2022-07-03 21:28 ` [PATCH v2 10/11] hw/openrisc: virt: pass random seed to fdt Stafford Horne
2022-07-04 10:22 ` Richard Henderson
2022-07-03 21:28 ` [PATCH v2 11/11] docs/system: openrisc: Add OpenRISC documentation Stafford Horne
2022-07-04 10:25 ` Richard Henderson
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