From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDuNZ-0000Iz-Ms for qemu-devel@nongnu.org; Fri, 17 Jun 2016 10:04:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bDuNY-0005jg-GZ for qemu-devel@nongnu.org; Fri, 17 Jun 2016 10:04:13 -0400 References: <1466169069-29375-1-git-send-email-real@ispras.ru> <1466169069-29375-12-git-send-email-real@ispras.ru> From: Paolo Bonzini Message-ID: <4c150d1b-05f5-db66-5a06-dcbe8b8baece@redhat.com> Date: Fri, 17 Jun 2016 16:03:58 +0200 MIME-Version: 1.0 In-Reply-To: <1466169069-29375-12-git-send-email-real@ispras.ru> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 11/13] ICH9 LPC: move call of isa_bus_irqs to 'realize' method List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Efimov Vasily , qemu-devel@nongnu.org Cc: John Snow , qemu-block@nongnu.org, Gerd Hoffmann , "Michael S. Tsirkin" , Kevin Wolf , Max Reitz , Richard Henderson , Eduardo Habkost , Peter Maydell , Kirill Batuzov On 17/06/2016 15:11, Efimov Vasily wrote: > The isa_bus_irqs function initializes ISA bus IRQ array pointer with sp= ecified > value. >=20 > Previously the ICH9 LPC bridge model did not have its own IRQs but > only IRQ pointer cache. And same GSI were used for ISA bus and other so= urces > behind the bridge (PCI, SCI). Hence, the pc_q35_init was only possible = place to > setup both ISA bus IRQs and the bridge IRQ cache. >=20 > As a result, the call of isa_bus_irqs was made from pc_q35_init. >=20 > Now the ICH9 LPC bridge has its own output IRQs which are connected to = GSI. The > output IRQs are already used to route IRQs from PCI and SCI. >=20 > The patch makes the ICH9 LPC bridge output IRQs to used for ISA bus too= . >=20 > Signed-off-by: Efimov Vasily > --- > hw/i386/pc_q35.c | 3 --- > hw/isa/lpc_ich9.c | 2 ++ > 2 files changed, 2 insertions(+), 3 deletions(-) >=20 > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c > index a1fad2b..4661be2 100644 > --- a/hw/i386/pc_q35.c > +++ b/hw/i386/pc_q35.c > @@ -200,9 +200,6 @@ static void pc_q35_init(MachineState *machine) > pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq); > isa_bus =3D ich9_lpc->isa_bus; > =20 > - /*end early*/ > - isa_bus_irqs(isa_bus, gsi); > - > if (kvm_pic_in_kernel()) { > i8259 =3D kvm_i8259_init(isa_bus); > } else if (xen_enabled()) { > diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c > index 1e8e0e4..798d9e7 100644 > --- a/hw/isa/lpc_ich9.c > +++ b/hw/isa/lpc_ich9.c > @@ -639,6 +639,8 @@ static void ich9_lpc_realize(PCIDevice *d, Error **= errp) > =20 > qdev_init_gpio_out(dev, lpc->pic, ISA_NUM_IRQS); > qdev_init_gpio_out(dev, lpc->ioapic, IOAPIC_NUM_PINS); > + > + isa_bus_irqs(isa_bus, lpc->pic); The modeling here was weird. ICH9 does not need both ->pic and ->ioapic, it can make do with just a 24-entry GSI array. If you change that in the previous patch, this one makes much more sense. As it is now, it seems like the ISA bus will not deliver interrupts to the IOAPIC, and that makes no sense. Thanks, Paolo > } > =20 > static bool ich9_rst_cnt_needed(void *opaque) >=20