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Iglesias" , Marcel Apfelbaum , Paolo Bonzini Date: Wed, 23 Oct 2024 02:16:49 +0200 In-Reply-To: <6b18238b-f9c3-4046-964f-de16dc30d26e@linaro.org> References: <20241022105614.839199-1-alex.bennee@linaro.org> <20241022105614.839199-8-alex.bennee@linaro.org> <6b18238b-f9c3-4046-964f-de16dc30d26e@linaro.org> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.52.4 (3.52.4-1.fc40) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: H5mvpg5WpP0LgFN83-PfKKlyGVf_CLmb X-Proofpoint-ORIG-GUID: bhM4KN_iLhtvPV9j9L2Gh6SjUqCU3ZM7 Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 adultscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410220156 Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, 2024-10-22 at 13:36 -0700, Pierrick Bouvier wrote: > On 10/22/24 03:56, Alex Benn=C3=A9e wrote: > > From: Ilya Leoshkevich > >=20 > > commit f025692c992c ("accel/tcg: Clear PAGE_WRITE before > > translation") > > fixed cross-modifying code handling, but did not add a test. The > > changed code was further improved recently [1], and I was not sure > > whether these modifications were safe (spoiler: they were fine). > >=20 > > Add a test to make sure there are no regressions. > >=20 > > [1] > > https://lists.gnu.org/archive/html/qemu-devel/2022-09/msg00034.html > >=20 > > Signed-off-by: Ilya Leoshkevich > > Message-Id: <20241001150617.9977-1-iii@linux.ibm.com> > > Signed-off-by: Alex Benn=C3=A9e > > --- > > =C2=A0 tests/tcg/x86_64/cross-modifying-code.c | 80 > > +++++++++++++++++++++++++ > > =C2=A0 tests/tcg/x86_64/Makefile.target=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 |=C2=A0 4 ++ > > =C2=A0 2 files changed, 84 insertions(+) > > =C2=A0 create mode 100644 tests/tcg/x86_64/cross-modifying-code.c > >=20 > > diff --git a/tests/tcg/x86_64/cross-modifying-code.c > > b/tests/tcg/x86_64/cross-modifying-code.c > > new file mode 100644 > > index 0000000000..2704df6061 > > --- /dev/null > > +++ b/tests/tcg/x86_64/cross-modifying-code.c > > @@ -0,0 +1,80 @@ > > +/* > > + * Test patching code, running in one thread, from another thread. > > + * > > + * Intel SDM calls this "cross-modifying code" and recommends a > > special > > + * sequence, which requires both threads to cooperate. > > + * > > + * Linux kernel uses a different sequence that does not require > > cooperation and > > + * involves patching the first byte with int3. > > + * > > + * Finally, there is user-mode software out there that simply uses > > atomics, and > > + * that seems to be good enough in practice. Test that QEMU has no > > problems > > + * with this as well. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +void add1_or_nop(long *x); > > +asm(".pushsection .rwx,\"awx\",@progbits\n" > > +=C2=A0=C2=A0=C2=A0 ".globl add1_or_nop\n" > > +=C2=A0=C2=A0=C2=A0 /* addq $0x1,(%rdi) */ > > +=C2=A0=C2=A0=C2=A0 "add1_or_nop: .byte 0x48, 0x83, 0x07, 0x01\n" > > +=C2=A0=C2=A0=C2=A0 "ret\n" > > +=C2=A0=C2=A0=C2=A0 ".popsection\n"); > > + > > +#define THREAD_WAIT 0 > > +#define THREAD_PATCH 1 > > +#define THREAD_STOP 2 > > + > > +static void *thread_func(void *arg) > > +{ > > +=C2=A0=C2=A0=C2=A0 int val =3D 0x0026748d; /* nop */ > > + > > +=C2=A0=C2=A0=C2=A0 while (true) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 switch (__atomic_load_n((in= t *)arg, __ATOMIC_SEQ_CST)) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case THREAD_WAIT: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bre= ak; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case THREAD_PATCH: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 val= =3D __atomic_exchange_n((int *)&add1_or_nop, val, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 __ATOMIC_SEQ_CST); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bre= ak; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 case THREAD_STOP: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ret= urn NULL; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 default: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ass= ert(false); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 __b= uiltin_unreachable(); >=20 > Use g_assert_not_reached() instead. > checkpatch emits an error for it now. Is there an easy way to include glib from testcases? It's located using meson, and I can't immediately see how to push the respective compiler flags to the test Makefiles - this seems to be currently handled by configure writing to $config_target_mak. [...]