From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v1 05/23] riscv: Add the tcg-target header file
Date: Wed, 12 Dec 2018 17:23:08 -0600 [thread overview]
Message-ID: <4c5a2e04-2c85-9c46-b807-31b447da8730@linaro.org> (raw)
In-Reply-To: <2560616ffb8a0e8c3001e3c5490c8bc1463468d0.1544643238.git.alistair.francis@wdc.com>
On 12/12/18 1:43 PM, Alistair Francis wrote:
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ddfeb32c6c..aa88ee176e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -262,6 +262,7 @@ S: Maintained
> F: target/riscv/
> F: hw/riscv/
> F: include/hw/riscv/
> +F: tcg/riscv/
This section is for RISC-V the target.
Your new entry belongs in RISC-V the TCG host.
See the "Tiny Code Generator (TCG)" header.
r~
next prev parent reply other threads:[~2018-12-12 23:23 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-12 19:42 [Qemu-devel] [PATCH v1 00/23] Add RISC-V TCG backend support Alistair Francis
2018-12-12 19:43 ` [Qemu-devel] [PATCH v1 01/23] elf.h: Add the RISCV ELF magic numbers Alistair Francis
2018-12-12 19:43 ` [Qemu-devel] [PATCH v1 02/23] linux-user: Add host dependency for RISC-V 32-bit Alistair Francis
2018-12-12 19:43 ` [Qemu-devel] [PATCH v1 03/23] linux-user: Add host dependency for RISC-V 64-bit Alistair Francis
2018-12-12 19:43 ` [Qemu-devel] [PATCH v1 04/23] exec: Add RISC-V GCC poison macro Alistair Francis
2018-12-12 19:43 ` [Qemu-devel] [PATCH v1 05/23] riscv: Add the tcg-target header file Alistair Francis
2018-12-12 23:23 ` Richard Henderson [this message]
2018-12-12 19:43 ` [Qemu-devel] [PATCH v1 06/23] riscv: Add the tcg target registers Alistair Francis
2018-12-12 19:43 ` [Qemu-devel] [PATCH v1 07/23] riscv: tcg-target: Add support for the constraints Alistair Francis
2018-12-12 19:44 ` [Qemu-devel] [PATCH v1 08/23] riscv: tcg-target: Add the immediate encoders Alistair Francis
2018-12-12 19:44 ` [Qemu-devel] [PATCH v1 09/23] riscv: tcg-target: Add the instruction emitters Alistair Francis
2018-12-12 19:44 ` [Qemu-devel] [PATCH v1 10/23] riscv: tcg-target: Add the relocation functions Alistair Francis
2018-12-12 19:44 ` [Qemu-devel] [PATCH v1 11/23] riscv: tcg-target: Add the mov and movi instruction Alistair Francis
2018-12-12 19:44 ` [Qemu-devel] [PATCH v1 12/23] riscv: tcg-target: Add the extract instructions Alistair Francis
2018-12-12 19:44 ` [Qemu-devel] [PATCH v1 13/23] riscv: tcg-target: Add the out load and store instructions Alistair Francis
2018-12-12 19:45 ` [Qemu-devel] [PATCH v1 14/23] riscv: tcg-target: Add the add2 and sub2 instructions Alistair Francis
2018-12-12 19:45 ` [Qemu-devel] [PATCH v1 15/23] riscv: tcg-target: Add branch and jump instructions Alistair Francis
2018-12-12 19:45 ` [Qemu-devel] [PATCH v1 16/23] riscv: tcg-target: Add slowpath load and store instructions Alistair Francis
2018-12-12 19:45 ` [Qemu-devel] [PATCH v1 17/23] riscv: tcg-target: Add direct " Alistair Francis
2018-12-12 19:45 ` [Qemu-devel] [PATCH v1 18/23] riscv: tcg-target: Add the out op decoder Alistair Francis
2018-12-12 19:45 ` [Qemu-devel] [PATCH v1 19/23] riscv: tcg-target: Add the prologue generation and register the JIT Alistair Francis
2018-12-12 19:45 ` [Qemu-devel] [PATCH v1 20/23] riscv: tcg-target: Add the target init code Alistair Francis
2018-12-12 19:46 ` [Qemu-devel] [PATCH v1 21/23] tcg: Add RISC-V cpu signal handler Alistair Francis
2018-12-12 19:46 ` [Qemu-devel] [PATCH v1 22/23] dias: Add RISC-V support Alistair Francis
2018-12-12 19:46 ` [Qemu-devel] [PATCH v1 23/23] configure: Add support for building RISC-V host Alistair Francis
2018-12-12 23:33 ` [Qemu-devel] [PATCH v1 00/23] Add RISC-V TCG backend support Richard Henderson
2018-12-13 0:41 ` Alistair Francis
2018-12-13 2:48 ` no-reply
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